A printed circuit board includes a first insulating layer; an external connection pad embedded in a first surface of the first insulating layer and having a first externally exposed surface disposed at substantially the same level as the first surface of the first insulating layer; a second insulating layer disposed on a second surface of the first insulating layer and having a first surface in contact with the second surface of the first insulating layer; and a first wiring pattern embedded in the second insulating layer and exposed from the first surface of the second insulating layer to be in contact with a second externally exposed surface of the external connection pad opposing the first externally exposed surface.

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

An integrated circuit (IC) package includes an interconnect comprising patches of unoxidized metal that are circumscribed by a region of roughened metal formed of oxidized metal. The IC package also includes a die mounted on the interconnect. The die is conductively coupled to at least a subset of the patches of unoxidized metal.

A circuit backplane of a display panel, a method for manufacturing the same, and a display panel are provided. The circuit backplane includes a substrate and a plurality of circuit regions on the substrate. Each of the plurality of circuit regions includes a cathode soldered electrode, an anode soldered electrode, and a flow blocking island that are on the substrate. The flow blocking island is between the cathode soldered electrode and the anode soldered electrode, and in a thickness direction of the circuit backplane, a height of the flow blocking island is greater than each of a height of the cathode soldered electrode and a height of the anode soldered electrode.

A packaging structure includes a semiconductor chip and conductive connection pillars. Each of the conductive connection pillars has a first surface and a second surface opposite to the first surface, and the first surfaces of the conductive connection pillars are fixed to a surface of the semiconductor chip. The packaging structure also includes a carrier plate. The carrier plate is disposed opposite to the semiconductor chip. The conductive connection pillars are located between the semiconductor chip and the carrier plate, and the second surfaces face the carrier plate. The packaging structure further includes solder layers located between the carrier plate and the second surfaces, and a barrier layer located on the surface of the carrier plate around the solder layers.

A light emitting package is provided, the light emitting package includes a carrier having a main part that has multiple chip bonding regions, and each the chip bonding regions has two neighboring conductive parts. An insulating part is disposed on the main part and portion of the two neighboring conductive parts, and multiple hollow-out structures are formed by the insulating part and corresponded in position to the chip bonding regions. Each of the hollow-out structures has a side wall that surrounds the chip bonding regions, and the portion of the tops of the two neighboring conductive parts are exposed from a bottom portion of the hollow-out structure, and multiple light emitting chips are disposed onto the chip bonding surfaces.

A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher. The surface treatment includes sandblasting.

Manufacturing of flip-chip type assemblies is provided, and includes forming one or more contact elements of electrically conductive material on a carrier surface of at least one chip carrier, providing a restrain structure around the contact elements, depositing solder material on the contact elements and/or on one or more terminals of electrically conductive material on a chip surface of at least one integrated circuit chip, and placing the chip with each terminal facing corresponding contact elements. Further, the method includes soldering each terminal to the corresponding contact element by a soldering material, the soldering material being restrained during a soldering of the terminals to the contact elements by the restrain structure, and forming one or more heat dissipation elements of thermally conductive material on the carrier surface for facing the chip surface displaced from the terminals, where the one or more heat dissipation elements are free of any solder mask.

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

A printed circuit board includes a first insulating layer; an external connection pad embedded in a first surface of the first insulating layer and having a first externally exposed surface disposed at substantially the same level as the first surface of the first insulating layer; a second insulating layer disposed on a second surface of the first insulating layer and having a first surface in contact with the second surface of the first insulating layer; and a first wiring pattern embedded in the second insulating layer and exposed from the first surface of the second insulating layer to be in contact with a second externally exposed surface of the external connection pad opposing the first externally exposed surface.