A method for forming a micro bump includes the following operations. A chip at least including a silicon substrate and a Through Silicon Via (TSV) penetrating through the silicon substrate is provided. A conductive layer having a first preset size in a first direction is formed in the TSV, the first direction being a thickness direction of the silicon substrate. A connecting layer having a second preset size in the first direction is formed on a surface of the conductive layer in the TSV, where a sum of the first preset size and the second preset size is equal to an initial size of the TSV in the first direction. The silicon substrate is processed to expose the connecting layer, for forming a micro bump corresponding to the TSV.

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

A system and method of using electrochemical additive manufacturing to add interconnection features, such as wafer bumps or pillars, or similar structures like heatsinks, to a plate such as a silicon wafer. The plate may be coupled to a cathode, and material for the features may be deposited onto the plate by transmitting current from an anode array through an electrolyte to the cathode. Position actuators and sensors may control the position and orientation of the plate and the anode array to place features in precise positions. Use of electrochemical additive manufacturing may enable construction of features that cannot be created using current photoresist-based methods. For example, pillars may be taller and more closely spaced, with heights of 200 μm or more, diameters of 10 μm or below, and inter-pillar spacing below 20 μm. Features may also extend horizontally instead of only vertically, enabling routing of interconnections to desired locations.

A system and method of using electrochemical additive manufacturing to add interconnection features, such as wafer bumps or pillars, or similar structures like heatsinks, to a plate such as a silicon wafer. The plate may be coupled to a cathode, and material for the features may be deposited onto the plate by transmitting current from an anode array through an electrolyte to the cathode. Position actuators and sensors may control the position and orientation of the plate and the anode array to place features in precise positions. Use of electrochemical additive manufacturing may enable construction of features that cannot be created using current photoresist-based methods. For example, pillars may be taller and more closely spaced, with heights of 200 μm or more, diameters of 10 μm or below, and inter-pillar spacing below 20 μm. Features may also extend horizontally instead of only vertically, enabling routing of interconnections to desired locations.

Discussed generally herein are methods and devices including or providing a redistribution layer device without under ball metallization. A device can include a substrate, electrical interconnect circuitry in the substrate, redistribution layer (RDL) circuitry electrically connected to the electrical interconnect circuitry, a conductive bump electrically connected to the RDL circuitry, the conductive bump interfacing directly with the RDL circuitry, and a sheet molding material over the substrate.

A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an active interposer including a programmable unit, a first memory die positioned above the active interposer and including a storage unit, and a first logic die positioned below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an active interposer including a programmable unit, a first memory die positioned above the active interposer and including a storage unit, and a first logic die positioned below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled.

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and a metal holder. The substrate includes at least one bonding pad disposed adjacent to its surface and the metal holder is disposed adjacent to the bonding pad.