Provided is a method for producing a joined body, the method including a first step of preparing a laminated body which includes a first member having a metal pillar provided on a surface thereof, a second member having an electrode pad provided on a surface thereof, and a joining material provided between the metal pillar and the electrode pad and containing metal particles and an organic compound, and a second step of heating the laminated body to sinter the joining material at a predetermined sintering temperature, in which the joining material satisfies the condition of the following Formula (I):
(M.sub.1−M.sub.2)/M.sub.1×100≥1.0  (I)
[in Formula (I), M.sub.1 represents a mass of the joining material when a temperature of the joining material reaches the sintering temperature in the second step, and M.sub.2 represents a non-volatile content in the joining material.]

Provided is a method for producing a joined body, the method including a first step of preparing a laminated body which includes a first member having a metal pillar provided on a surface thereof, a second member having an electrode pad provided on a surface thereof, and a joining material provided between the metal pillar and the electrode pad and containing metal particles and an organic compound, and a second step of heating the laminated body to sinter the joining material at a predetermined sintering temperature, in which the joining material satisfies the condition of the following Formula (I):
(M.sub.1−M.sub.2)/M.sub.1×100≥1.0  (I)
[in Formula (I), M.sub.1 represents a mass of the joining material when a temperature of the joining material reaches the sintering temperature in the second step, and M.sub.2 represents a non-volatile content in the joining material.]

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.

A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.