A method of forming a semiconductor package includes attaching a first package component to a first carrier; attaching a second package component to the first carrier, the second package component laterally displaced from the first package component; attaching a third package component to the first package component, the third package component being electrically connected to the first package component; removing the first carrier from the first package component and the second package component; after removing the first carrier, performing a first circuit probe test on the second package component to obtain first test data of the second package component; and comparing the first test data of the second package component with prior data of the second package component.

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

A height of a vertical wire interconnection bonded onto a substrate is measured by first capturing a top view of the vertical wire interconnection and identifying a position of a tip end of the vertical wire interconnection from the top view. A conductive probe is located over the tip end of the vertical wire interconnection, and is lowered towards the vertical wire interconnection until an electrical connection is made between the conductive probe and the tip end of the vertical wire interconnection. A contact height at which the electrical connection is made may thus be determined, wherein the contact height corresponds to the height of the vertical wire interconnection.

A ball disposition system includes a ball adsorption device, and a ball guide plate providing a ball guide hole. The ball adsorption device includes an adsorption plate providing an adsorption hole extending in a first direction, and a pin extending in the first direction, a portion of the pin inserted in the adsorption hole. The ball guide plate is located beyond the adsorption plate in the first direction.

A dipping apparatus includes a squeegee device and a plate for forming a flux film out of flux. A surface of the plate has a rough surface with a nano-level arithmetically average roughness. The dipping apparatus is configured in such a way that the squeegee device and the plate are moved relatively to each other, and the flux is fed from the squeegee device to the rough surface of the plate.

An object is to allow for simple measurement of a bump height. There is provided a device for measuring a bump height comprising: a light sensor provided with a light source and a light-receiving element and configured to irradiate a substrate including a seed layer, a resist layer formed on the seed layer and a bump formed in an opening of the resist layer, with light emitted from the light source and to detect reflected light that is reflected from the seed layer via the resist layer and reflected light that is reflected from the bump, by the light-receiving element; and a control device configured to calculate a height of the bump relative to the seed layer, based on the reflected light from the seed layer and the reflected light from the bump and to subtract an error caused by a refractive index of the resist layer from the height of the bump calculated based on the reflected lights, so as to correct the height of the bump.

A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.

A semiconductor package manufacturing method is provided. The semiconductor package manufacturing method which uses a semiconductor package manufacturing apparatus including a chuck, a solder device configured to attach solder balls to a substrate provided on the chuck, and a scanning device configured to provide information about a shape of the substrate to the chuck, wherein the chuck comprises an adsorbing portion comprising a plurality of divided regions, each of which is configured to adsorb the substrate, and a driver configured to drive each of the plurality of divided regions, the semiconductor package manufacturing method comprising driving each of the plurality of divided regions to correspond to the shape of the substrate based on the information using the driver.

A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures includes a substrate and a superconducting trace. Additionally, each of the semiconductor structures includes a passivation layer and one or more under bump metal (UBM) structures. The cryogenic electronic package also includes one or more superconducting and/or conventional metal interconnect structures disposed between selected ones of the at least two superconducting semiconductor structures. The interconnect structures are electrically coupled to respective ones of the UBM structures of the semiconductor structures to form one or more electrical connections between the semiconductor structures. A method of fabricating a cryogenic electronic package is also provided.

The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.