An electronic component includes an electronic component main body including a first surface, a signal bump electrode arranged on the first surface to protrude from the first surface of the electronic component main body, and a protective film provided with an opening through which a part of the signal bump electrode is exposed, the protective film being arranged to cover a portion of the signal bump electrode other than a portion exposed through the opening. The protective film includes a first insulating film, a second insulating film that covers the first insulating film, and a first shield film arranged as lying between the first insulating film and the second insulating film. The first shield film is covered with at least one of the first insulating film and the second insulating film so as not to be exposed at an inner surface of the opening.

A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The wafer-level pulling method further includes softening the plurality of solder bumps; and stretching the plurality of softened solder bumps.

A semiconductor device includes a first die, a second die bonding to the first die thereby forming a bonding interface, and a pad of the first die and exposed from a polymeric layer of the first die. The semiconductor device further has a conductive material on the pad and extended from the pad in a direction parallel to a stacking direction of the first die and the second die. In the semiconductor device, the conductive material extended to a top surface, which is vertically higher than a backside of the second die, wherein the backside is a surface opposite to the bonding interface.

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.

A semiconductor package of a pin-grid-array type includes a bump pad on a first substrate, a metal socket on a second substrate, a core material for reverse reflow on the bump pad, and solder paste or a solder bump forming a solder layer on the core material for reverse reflow. The solder paste or the solder bump is in contact with the bump pad. The core material for reverse reflow and the solder paste or the solder bump bonded to the core material for reverse reflow are used as a pin and detachably attached to the metal socket. The core material for reverse reflow includes a core, a first metal layer directly coated on the core, and a second metal layer directly coated on the first metal layer.

A semiconductor package of a pin-grid-array type includes a bump pad on a first substrate, a metal socket on a second substrate, a core material for reverse reflow on the bump pad, and solder paste or a solder bump forming a solder layer on the core material for reverse reflow. The solder paste or the solder bump is in contact with the bump pad. The core material for reverse reflow and the solder paste or the solder bump bonded to the core material for reverse reflow are used as a pin and detachably attached to the metal socket. The core material for reverse reflow includes a core, a first metal layer directly coated on the core, and a second metal layer directly coated on the first metal layer.

An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

A semiconductor composite structure includes an electrically conductive bump, and a patterned bonding layer. The electrically conductive bump includes a body portion for being electrically connected to a metal layer of a semiconductor substrate, and a contact portion disposed on the body portion opposite to the metal layer. The patterned bonding layer is disposed on the contact portion opposite to the body portion, and includes an electrically conductive portion and a recess portion depressed relative to the electrically conductive portion. An etching selectivity ratio of the conductive portion relative to the contact portion is greater than 1. A method for making the semiconductor composite structure and a semiconductor device are also disclosed.