A package substrate according to an embodiment includes an insulating layer; a first outer circuit pattern disposed on an upper surface of the insulating layer; a second outer circuit pattern disposed under a lower surface of the insulating layer; a first connection portion disposed on an upper surface of a first-first circuit pattern of the first outer circuit pattern; a first contact portion disposed on the first connection portion; a first device disposed on the first connection portion through the first contact portion; a second contact portion disposed under a lower surface of a second-first circuit pattern of the second outer circuit pattern; a second device attached to the second-first circuit pattern through the second contact portion; and a second connection portion disposed under a lower surface of a second-second circuit pattern of the second outer circuit pattern; wherein the first connection portion is disposed with a first width and a first interval, and wherein the second connection portion is disposed with a second width greater than the first width and a second interval greater than the first interval.

Provided are a Sn—Bi—In-based low melting-point joining member used in a Pb-free electroconductive joining method in mounting a semiconductor component, and is usable for low-temperature joining, and a manufacturing method therefor.

A Sn—Bi—In-based low melting-point joining member, including a Sn—Bi—In alloy that has a composition within a range represented by a quadrangle in a Sn—Bi—In ternary phase diagram, a first quadrangle having four vertices including: Point 1 (1, 69, 30), Point 2 (26, 52, 22), Point 3 (40, 10, 50), and Point 4 (1, 25, 74), where Point (x, y, z) is defined as a point of x mass % Sn, y mass % Bi and z mass % In, and that also has a melting point of 60 to 110° C. As well as a method for producing a Sn—Bi—In-based low melting-point joining member, including a plating step of forming a plated laminate on an object to be plated, the plated laminate including a laminated plating layer obtained by performing Sn plating, Bi plating, and In plating respectively such that the laminated plating layer has a composition within the range represented by the first quadrangle.

A semiconductor device includes a substrate having a plurality of pads on a surface of the substrate, a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate, a first resin layer between the surface of the substrate and the semiconductor chip, a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps, and a third resin layer on the substrate and above the semiconductor chip.

A cryogenic under bump metallization (UBM) stack includes an adhesion and barrier layer and a conductive pillar on the adhesion and barrier layer. The conductive pillar functions as a solder wetting layer of the UBM stack and has a thickness. An indium superconducting solder bump is on the conductive pillar. The thickness of the conductive pillar is sufficient to prevent intermetallic regions, which form in the conductive pillar at room temperature due to interdiffusion, from extending through the entire thickness of the conductive pillar to maintain the structural integrity of the UBM stack. The indium (In) solder bump may be formed through electroplating, with the conductive pillar being copper (Cu) and the adhesion and barrier layer being titanium tungsten (TiW) and a thin seed layer of copper (Cu), or a layer of titanium (Ti). The UBM stack eliminates the need for magnetic materials such as nickel (Ni) in the stack, making the stack suitable for cryogenic applications.

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

A semiconductor structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The second semiconductor die is bonded to the first bonding structure of the first semiconductor die. The first bonding structure includes a first dielectric layer, a second dielectric layer covering the first dielectric layer, and first conductors embedded in the first dielectric layer and the second dielectric layer, wherein each of the first conductors includes a first conductive barrier layer covering the first dielectric layer and a first conductive pillar disposed on the first conductive barrier layer, and the first conductive pillars are in contact with the second dielectric layer.

The present disclosure provides a method for manufacturing a semiconductor structure. The method includes providing a substrate having a redistribution layer (RDL); disposing an etch stop layer over a RDL; patterning the dielectric layer and the etch stop layer; disposing a first seed layer over the etch stop layer and a portion of the dielectric layer that is exposed through the etch stop layer; disposing a second patterned photoresist over the first seed layer; disposing a conductive material over a portion of the first seed layer that is exposed through the second patterned photoresist; removing the second patterned photoresist; removing the etch stop layer; and removing a portion of the conductive material that protrudes from the dielectric layer to form a bonding pad adjacent to the conductive plug and surrounded by the dielectric layer.

An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

The present disclosure provides a semiconductor structure including a substrate; a redistribution layer (RDL) disposed over the substrate, and including a dielectric layer over the substrate, a conductive plug extending within the dielectric layer, and a bonding pad adjacent to the conductive plug and surrounded by the dielectric layer; and a conductive bump disposed over the conductive plug, wherein the bonding pad is at least partially in contact with the conductive plug and the conductive bump. Further, a method of manufacturing the semiconductor structure is also provided.