Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.

Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad.

Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad.

Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.

A light emitting device including a protection layer including a first area and a second area having a greater thickness than the first area, a light emitting stacked structure including a plurality of semiconductor layers sequentially disposed one over another along a first direction on the first area of the protection layer, a plurality of via patterns electrically connected to the light emitting stacked structure and having a length along the first direction, and a plurality of pads electrically connected to the light emitting stacked structure through the via patterns, respectively, in which the second area of the protection layer does not overlap the light emitting stacked structure, and at least portion of the pads overlaps the second area of the protection layer and one of the via patterns.

A light emitting device including a protection layer including a first area and a second area having a greater thickness than the first area, a light emitting stacked structure including a plurality of semiconductor layers sequentially disposed one over another along a first direction on the first area of the protection layer, a plurality of via patterns electrically connected to the light emitting stacked structure and having a length along the first direction, and a plurality of pads electrically connected to the light emitting stacked structure through the via patterns, respectively, in which the second area of the protection layer does not overlap the light emitting stacked structure, and at least portion of the pads overlaps the second area of the protection layer and one of the via patterns.

A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 μm or less.

A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.

A semiconductor device package includes a redistribution layer, a first semiconductor device, a second semiconductor device, a first insulation body, and a second insulation body. The first semiconductor device can be disposed on the redistribution layer. The second semiconductor device can be stacked on the first semiconductor device. The first insulation body can be disposed between the first semiconductor device and the second semiconductor device. The first insulation body may have a number of first particles. The second insulation body can encapsulate the first insulation body and have a number of second particles. One of the number of first particles can have a flat surface.