A package structure including a redistribution circuit structure, an insulator, a plurality of conductive connection pieces, a first chip, a second chip, an encapsulant, a third chip, and a plurality of conductive terminals is provided. The redistribution circuit structure has first and second connection surfaces opposite to each other. The insulator is embedded in and penetrates the redistribution circuit structure. The conductive connection pieces penetrate the insulator. The first and second chips are disposed on the first connection surface. The encapsulant is disposed on the redistribution circuit structure and at least laterally covers the first and second chips. The third chip is disposed on the second connection surface and electrically connected to the first and second chips through the conductive connection pieces. The conductive terminals are disposed on the second connection surface and electrically connected to the first chip or the second chip through the redistribution circuit structure.

A package structure including a first chip, a second chip, a dielectric body, a third chip, an encapsulant, a first conductive terminal, and a circuit layer is provided. The dielectric body covers the first chip and the second chip. The third chip is disposed on the dielectric body such that a third active surface thereof faces a first active surface of the first chip or a second active surface of the second chip. The encapsulant covers the third chip. The first conductive terminal is disposed on the dielectric body and is opposite to the third chip. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first chip, the second chip, or the third chip is electrically connected to the first conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body.

A method of yield prejudgment and bump re-assignment for a die is provided. The die includes a plurality of areas. Each area is electrically connected to a substrate through a corresponding bump. The successful-connection probability of each area is prejudged. The die is divided into a signal region and a short-circuit region according to the successful-connection probabilities. The positions of the bumps are arranged so that signal bumps are disposed in the signal region and power bumps are disposed in the short region.

A method of yield prejudgment and bump re-assignment for a die is provided. The die includes a plurality of areas. Each area is electrically connected to a substrate through a corresponding bump. The successful-connection probability of each area is prejudged. The die is divided into a signal region and a short-circuit region according to the successful-connection probabilities. The positions of the bumps are arranged so that signal bumps are disposed in the signal region and power bumps are disposed in the short region.

The present invention discloses a lead structure of the circuit, which comprises a first lead and a second lead. The first lead includes a first bump connecting part and a first lead segment. The first lead segment is connected to the first bump connecting part. The width of the first lead segment is smaller than the width of the first bump connecting part. The second lead is adjacent to the first lead and there is a lead gap therebetween. The second lead also includes a second bump connecting part and a first lead segment. The first lead segment of the second lead is connected to the second bump connecting part. The second bump connecting part and the first bump connecting part are arranged staggeredly. The second bump connecting part is adjacent to the first lead segment of the first lead.

A semiconductor package according to an example includes a base die having a first surface and a second surface opposite each other; a first group of core dies stacked on the first surface of the base die and electrically connected to the base die; a mount member facing the second surface of the base die; a second group of core dies between the base die and the mount member, the second group of core dies being stacked on the second surface of the base die and electrically connected to the base die; and an interface for an electrical connection between the base die and the mount member.