Patent classifications
H
ELECTRICITY
Load children
H01
ELECTRIC ELEMENTS
Load children
H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
Load children
2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/18
High density interconnect [HDI] connectors; Manufacturing methods related thereto
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/23
Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/25
of a plurality of high density interconnect connectors
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/2511
the connectors being bonded to at least one common bonding area
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/25113
the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body
Filter patents View analytics View as hierarchy Open in page

H01L2224/25113

SEMICONDUCTOR PACKAGES USING PACKAGE IN PACKAGE SYSTEMS AND RELATED METHODS
20210242167 · 2021-08-05 · ·

Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

Semiconductor packages using package in package systems and related methods
11984424 · 2024-05-14 · ·

Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

Semiconductor packages using package in package systems and related methods
12417999 · 2025-09-16 · ·

Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.