This invention relates to a method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate with the following steps, especially the following sequence: forming a reservoir in a surface layer on the first contact surface, the first surface layer consisting at least largely of a native oxide material, at least partial filling of the reservoir with a first educt or a first group of educts, the first contact surface making contact with the second contact surface for formation of a prebond connection, forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt with a second educt contained in a reaction layer of the second substrate.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

One aspect is a logic power module, with at least one logic component, at least one power component and a substrate. The logic element and the power component are provided in separate areas on the substrate. The logic component on the substrate is provided by thick printed copper; and the power component is provided by a metal-containing thick-film layer, and, provided thereon, a metal foil.

A bonding member (10) includes surface-processed silver surfaces (11a, 11b).

A semiconductor device includes a semiconductor element having an NiV electrode and a conductor, the semiconductor element and the conductor being bonded via Sn-based lead-free solder. In the semiconductor device, an SnV compound layer and an (Ni, Cu)3Sn4 compound layer adjacent to the SnV compound are formed adjacent to an interface between the semiconductor element and the Sn-based lead-free solder. A manufacturing method for a semiconductor device according to the present invention includes: causing the Sn-based lead-free solder and the NiV electrode to react with each other to form an SnV layer and an (Ni, Cu)3Sn4 compound layer; and following formation of the SnV layer, leaving an unreacted layer of the NiV electrode, the unreacted layer having not reacted with the Sn-based lead-free solder, intact.

According to embodiments of the present disclosure, a semiconductor package is provided. The semiconductor package includes a substrate including a first surface and a second surface opposite to the first surface; and a plurality of lower pads on the second surface at different intervals. The semiconductor package further includes: a plurality of bumps attached to the plurality of lower pads; a first non-conductive film on the second surface of the substrate; and a second non-conductive film on the first non-conductive film. A plurality of regions are defined in the semiconductor package according to a separation distance between the plurality of bumps, such that each region of the plurality of regions includes respective bumps, from among the plurality of bumps, that have a respective separation distance between neighboring ones of the respective bumps within the region. A sum of thicknesses of the first and second non-conductive films is constant.

A wafer bonding method includes providing a first wafer including a first wafer surface, forming a first metal layer on the first wafer surface, and forming a first annular retaining wall structure including a first annular retaining wall and a second annular retaining wall surrounded by the first annular retaining wall. The first metal layer is formed between the first annular retaining wall and the second annular retaining wall. The method includes providing a second wafer including a second wafer surface, forming a second metal layer on the second wafer surface, and forming a second annular retaining wall structure including a third annular retaining wall and a fourth annular retaining wall surrounded by the third annular retaining wall. The second metal layer is formed between the third annular retaining wall and the fourth annular retaining wall. The method further includes bonding the first metal layer to the second metal layer.

A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.

A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.