A package structure and a manufacturing method thereof are provided. The package structure includes a carrier substrate, an integrated circuit (IC) die thermally coupled to the carrier substrate through a thermally conductive layer, an antenna pattern disposed over the carrier substrate and the IC die, a redistribution structure disposed between the antenna pattern and the IC die, and an underfill disposed below and thermally coupled to the carrier substrate. The antenna pattern is electrically coupled to the IC die.

Structures and methods are disclosed for fabricating optoelectronic solid state array devices. In one case a backplane and array of micro devices is aligned and connected through bumps.

A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer; assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.

A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

In at least one embodiment, the power semiconductor device (1) comprises: at least one support (2), at least one power semiconductor chip (24) is arranged on a support top side (20), a heat sink (3) having a heat sink top side (30), the at least one support (2) is arranged on the heat sink top side (30), and a mold body (4) of an electric insulating material in direct contact with the at least one support (2) and the heat sink (3),
wherein the mold body (4) fixes and presses the at least one support (2) onto the heat sink (3).

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.