A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 μm from each other to enable contact or direct-bonding between pads and vias with diameters under 5 μm at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives. A nanowire forming technique creates a nanoporous layer on conductive pads, creates nanowires within pores of the nanoporous layer, and removes at least part of the nanoporous layer to reveal a layer of nanowires less than 1 μm in height for direct bonding.

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

A semiconductor device includes a power semiconductor device, a circuit board, and an insulating substrate. The power semiconductor device includes contact pads. Adjacent ones of the contact pads are separated by one of a plurality of gaps. The circuit board includes traces for coupling with the contact pads of the power semiconductor device. The contact pads are physically attached to the traces. The insulating substrate is disposed between the circuit board and the power semiconductor device, where portions of the insulating substrate are disposed in the plurality of gaps, and where the insulating substrate has a monolithic structure.

A surface acoustic wave (SAW) filter package structure includes a dielectric substrate having a dielectric layer, a first patterned conductive layer, a second patterned conductive layer, and a conductive connection layer. The conductive connection layer is electrically connected between the first patterned conductive layer and the second patterned conductive layer, which are disposed at opposite sides of the dielectric layer. The second patterned conductive layer has a finger electrode portion. An active surface of a chip is faced toward the finger electrode portion. A polymer sealing frame is disposed between the chip and the dielectric substrate and surrounds the periphery of the chip to form a chamber together with the chip and the dielectric substrate. The mold sealing layer is disposed on the dielectric substrate and covers the chip and the polymer sealing frame. A manufacturing method of the SAW filter package structure is also disclosed.

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

A surface acoustic wave (SAW) filter package structure includes a dielectric substrate having a dielectric layer, a first patterned conductive layer, a second patterned conductive layer, and a conductive connection layer. The conductive connection layer is electrically connected between the first patterned conductive layer and the second patterned conductive layer, which are disposed at opposite sides of the dielectric layer. The second patterned conductive layer has a finger electrode portion. An active surface of a chip is faced toward the finger electrode portion. A polymer sealing frame is disposed between the chip and the dielectric substrate and surrounds the periphery of the chip to form a chamber together with the chip and the dielectric substrate. The mold sealing layer is disposed on the dielectric substrate and covers the chip and the polymer sealing frame. A manufacturing method of the SAW filter package structure is also disclosed.

An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

A surface acoustic wave (SAW) filter package structure includes a dielectric substrate having a dielectric layer, a first patterned conductive layer, a second patterned conductive layer, and a conductive connection layer. The conductive connection layer is electrically connected between the first patterned conductive layer and the second patterned conductive layer, which are disposed at opposite sides of the dielectric layer. The second patterned conductive layer has a finger electrode portion. An active surface of a chip is faced toward the finger electrode portion. A polymer sealing frame is disposed between the chip and the dielectric substrate and surrounds the periphery of the chip to form a chamber together with the chip and the dielectric substrate. The mold sealing layer is disposed on the dielectric substrate and covers the chip and the polymer sealing frame. A manufacturing method of the SAW filter package structure is also disclosed.

A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 μm from each other to enable contact or direct-bonding between pads and vias with diameters under 5 μm at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives. A nanowire forming technique creates a nanoporous layer on conductive pads, creates nanowires within pores of the nanoporous layer, and removes at least part of the nanoporous layer to reveal a layer of nanowires less than 1 μm in height for direct bonding.

An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.