Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.

A semiconductor package includes a plurality of first semiconductor structures that are stacked on a package substrate and are offset from each other in a first direction, and a plurality of first adhesive layers disposed between the first semiconductor structures. Each of the first semiconductor structures includes a first sub-chip and a second sub-chip in contact with a part of a top surface of the first sub-chip. The first adhesive layers are disposed between and are in contact with the first sub-chips. The first adhesive layers are spaced apart from the second sub-chips. A thickness of each of the first adhesive layers is less than a thickness of each of the second sub-chips. The thickness of the second sub-chip is in a range of about 13 μm to about 20 μm.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.

A COF package includes a substrate and a chip, composite bumps on the chip are bonded to leads on the substrate. Each of the composite bumps includes a raising strip, a UBM layer and a bonding layer. A bonding rib is formed on the bonding layer because of the raising strip and the UBM layer, and the bonding rib on each of the composite bumps can be inserted into each of the leads and surface-contact with each of the leads to increase weld length and bonding strength between the bonding layer and the leads and further reduce a force required for bonding the chip to the substrate in a flip-chip bonding process.

A semiconductor device assembly includes a die stack, a plurality of thermoset regions, and underfill material. The die stack includes at least first and second dies that each have a plurality of conductive interconnect elements on upper surfaces. A portion of the interconnect elements are connected to through-silicon vias that extend between the upper surfaces and lower surfaces of the associated dies. The plurality of thermoset regions each comprise a thin layer of thermoset material extending from the lower surface of the second die to the upper surface of the first die, and are laterally-spaced and discrete from each other. Each of the thermoset regions extends to fill an area between a plurality of adjacent interconnect elements of the first die. The underfill material fills remaining open areas between the interconnect elements of the first die.

An electrical device includes a substrate, an insulating layer supported by the substrate, and an electrically conductive vertical interconnect disposed in a via hole of the insulating layer. The insulating layer may be configured to provide a coefficient of thermal expansion (CTE) that is equal to or greater than a CTE of the vertical interconnect to thereby impart axial compressive forces at opposite ends of the interconnect. The vertical interconnect may be a hybrid interconnect structure including a low CTE conductor post having a pocket that contains a high CTE conductor contact. At low operating temperatures, the high CTE conductor contact is under tension due to the higher CTE, and thus the high CTE conductor contact relieves strain in the device by void expansion and elongation.

A semiconductor package structure includes an organic substrate having a first surface, a first recess depressed from the first surface, a first chip over the first surface and covering the first recess, thereby defining a first cavity enclosed by a back surface of the first chip and the first recess, and a second chip over the first chip. The first cavity is an air cavity or a vacuum cavity.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.

A semiconductor device package includes a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; and a dielectric layer surrounding the connection structure, wherein the dielectric layer and the second portion of the connection structure defines a space.