A power module substrate with a Ag underlayer of the invention includes: a circuit layer that is formed on one surface of an insulating layer; and a Ag underlayer that is formed on the circuit layer, in which the Ag underlayer is composed of a glass layer that is formed on the circuit layer side and a Ag layer that is formed by lamination on the glass layer, and regarding the Ag underlayer, in a Raman spectrum obtained by a Raman spectroscopy with incident light made incident from a surface of the Ag layer on a side opposite to the glass layer, when a maximum value of intensity in a wavenumber range of 3,000 cm.sup.−1 to 4,000 cm.sup.−1 indicated by I.sub.A, and a maximum value of intensity in a wavenumber range of 450 cm.sup.−1 to 550 cm.sup.−1 is indicated by I.sub.B, I.sub.A/I.sub.B is 1.1 or greater.

A printed circuit board assembly of an implantable medical device comprises a printed circuit board and a sensor device that is arranged at the printed circuit board and joined to the printed circuit board by way of an adhesive layer. It is provided in the process that the adhesive layer is formed of an adhesive compound in which glass spheres are embedded. In this way, a printed circuit board assembly is provided which, in a simple, inexpensive manner, allows a sensor device to be joined to a printed circuit board for installation in a medical device, with advantageous mechanical decoupling and improved process reliability.

Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

A printed circuit board assembly of an implantable medical device comprises a printed circuit board and a sensor device that is arranged at the printed circuit board and joined to the printed circuit board by way of an adhesive layer. It is provided in the process that the adhesive layer is formed of an adhesive compound in which glass spheres are embedded. In this way, a printed circuit board assembly is provided which, in a simple, inexpensive manner, allows a sensor device to be joined to a printed circuit board for installation in a medical device, with advantageous mechanical decoupling and improved process reliability.

Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass , and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

A printed circuit board assembly of an implantable medical device comprises a printed circuit board and a sensor device that is arranged at the printed circuit board and joined to the printed circuit board by way of an adhesive layer. It is provided in the process that the adhesive layer is formed of an adhesive compound in which glass spheres are embedded. In this way, a printed circuit board assembly is provided which, in a simple, inexpensive manner, allows a sensor device to be joined to a printed circuit board for installation in a medical device, with advantageous mechanical decoupling and improved process reliability.

A wafer-level packaging method and a package structure are provided. In the method, a first wafer is provided having first chips formed there-in. A surface of each first chip is integrated with a first electrode. A first dielectric layer is formed on the first wafer to expose each first electrode. Second chips are provided with a surface of each second chip integrated with a second electrode. A second dielectric layer is formed on the plurality of second chips to expose each second electrode. The second dielectric layer is positioned relative to the first dielectric layer. The second chips are bonded to the first wafer with each second chip aligned relative to one first chip to form a cavity there-between. A chip interconnection structure is formed in the cavity to electrically connect the first electrode with the second electrode. An encapsulation layer covers the second chips.

A wafer-level packaging method and a package structure are provided. In the method, a first wafer is provided having first chips formed there-in. A surface of each first chip is integrated with a first electrode. A first dielectric layer is formed on the first wafer to expose each first electrode. Second chips are provided with a surface of each second chip integrated with a second electrode. A second dielectric layer is formed on the plurality of second chips to expose each second electrode. The second dielectric layer is positioned relative to the first dielectric layer. The second chips are bonded to the first wafer with each second chip aligned relative to one first chip to form a cavity there-between. A chip interconnection structure is formed in the cavity to electrically connect the first electrode with the second electrode. An encapsulation layer covers the second chips.

A wafer-level packaging method and a package structure are provided. In the method, a first wafer is provided having first chips formed there-in. A surface of each first chip is integrated with a first electrode. A first dielectric layer is formed on the first wafer to expose each first electrode. Second chips are provided with a surface of each second chip integrated with a second electrode. A second dielectric layer is formed on the plurality of second chips to expose each second electrode. The second dielectric layer is positioned relative to the first dielectric layer. The second chips are bonded to the first wafer with each second chip aligned relative to one first chip to form a cavity there-between. A chip interconnection structure is formed in the cavity to electrically connect the first electrode with the second electrode. An encapsulation layer covers the second chips.