A driving backplane, a transfer method for a light-emitting diode chip (21), and a display apparatus. The driving backplane comprises: a base substrate (10), a driving circuit, a plurality of electromagnetic structures (13), and a plurality of contact electrodes (12). The plurality of electromagnetic structures (13) in the driving backplane are symmetrically arranged relative to a first straight line (L1) and a second straight line (L2). A current signal can be applied to each electromagnetic structure (13) by means of the driving circuit. Stress generated by a transfer carrier plate (20) according to the magnetic force of each electromagnetic structure (13) moves the transfer carrier plate (20). When the transfer carrier plate (20) is stress balanced in each direction parallel to the surface of the transfer carrier plate (20), the light-emitting diode chip (21) is precisely aligned to corresponding contact electrodes (12).

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

A solder material for use in electronic assembly, the solder material comprising: solder layers; and a core layer comprising a core material, the core layer being sandwiched between the solder layers, wherein: the thermal conductivity of the core material is greater than the thermal conductivity of the solder.

A solder material for use in electronic assembly, the solder material comprising: solder layers; and a core layer comprising a core material, the core layer being sandwiched between the solder layers, wherein: the thermal conductivity of the core material is greater than the thermal conductivity of the solder.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

Provided is a joint structure interposed between a semiconductor element and a substrate, the joint structure including: a Sn phase; Cu alloy particles containing P in an amount of 1 mass % or more and less than 7 mass %; and Ag particles, wherein the Cu alloy particles are each coated with a Cu.sub.6Sn.sub.5 layer, wherein the Ag particles are each coated with a Ag.sub.3Sn layer, wherein the Cu alloy particles and the Ag particles are at least partially bonded to each other through a Cu.sub.10Sn.sub.3 phase, wherein a total of addition amounts of the Cu alloy particles and the Ag particles is 25 mass % or more and less than 65 mass % with respect to the joint structure, and wherein a mass ratio of the addition amount of the Ag particles to the addition amount of the Cu alloy particles is 0.2 or more and less than 1.2.