Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/26
Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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H01L2224/28
Structure, shape, material or disposition of the layer connectors prior to the connecting process
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H01L2224/29
of an individual layer connector
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H01L2224/296
with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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H01L2224/29663
the principal constituent melting at a temperature of greater than 1550°C
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H01L2224/29673
Rhodium [Rh] as principal constituent
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H01L2224/29673

PACKAGE STRUCTURE AND PACKAGING METHOD
20250385211 · 2025-12-18 · ·

A package structure includes a substrate, a chip disposed on the substrate and having a backside surface away from the substrate, a heat sink disposed above the substrate and having a surface facing the back side surface, and a thermal interface material disposed between the chip and the heat sink. There is no organic adhesive between the chip and the heat sink. A method for forming the package structure is also provided.