H01L2224/30135

Method for fabricating an electronic device comprising forming an infused adhesive and a periperal ring

A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.

RADAR DEVICE

A radar device includes: a substrate including multiple high-frequency conductor layers arranged on a front surface; a semiconductor component in contact with the high-frequency conductor layers via conductive members; and an adhesive that bonds the semiconductor component to the front surface of the substrate. The semiconductor component has a bottom surface and a first side surface facing in a first direction. All the multiple high-frequency conductor layers include at least high-frequency conductor layers bending in a plane of the front surface and thereby extend, on the front surface, from inside ends facing the bottom surface to outside ends positioned in the first direction from the first side surface. The adhesive is in contact with the front surface except for the sites of the multiple high-frequency conductor layers formed and in contact with the side surfaces of the semiconductor component.

ELECTRONIC SUBSTRATE AND ELECTRONIC APPARATUS

An electronic substrate includes: a body having a mounting surface; an electronic component having an opposed surface facing the mounting surface; and an adhesive layer that bonds the electronic component to the mounting surface. The mounting surface has a storage recess that stores at least a part of the adhesive layer. The storage recess is located from a first area overlapping the opposed surface to a second area not overlapping the opposed surface in plan view.

Semiconductor device with a layered protection mechanism and associated systems, devices, and methods
11114415 · 2021-09-07 · ·

A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

METHOD FOR FABRICATING AN ELECTRONIC DEVICE AND A STACKED ELECTRONIC DEVICE

A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.

SEMICONDUCTOR DEVICE WITH A LAYERED PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
20200219851 · 2020-07-09 ·

A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

Method for fabricating an electronic device and a stacked electronic device

A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.

Semiconductor device with a layered protection mechanism and associated systems, devices, and methods
10615150 · 2020-04-07 · ·

A semiconductor device includes a first die; a second die attached over the first die; a first metal enclosure and a second metal enclosure both directly contacting and vertically extending between the first die and the second die, wherein the first metal enclosure peripherally encircles a set of one or more internal interconnects and the second metal enclosure peripherally encircles the first metal enclosure without directly contacting the first metal enclosure; a first enclosure connector electrically connecting the first metal enclosure to a first voltage level; a second enclosure connector electrically connecting the second metal enclosure to a second voltage level; and wherein the first metal enclosure, the second metal enclosure, the first enclosure connector, and the second enclosure connector are configured to provide an enclosure capacitance.

Semiconductor device

A semiconductor device according to an embodiment includes a semiconductor chip including a region having through holes; a substrate having a first opening larger than the region, the substrate containing a resin or a ceramic; a spacer provided between the semiconductor chip and the substrate, the spacer having a second opening larger than the region; a first bond provided between the semiconductor chip and the spacer; and a second bond provided between the spacer and the substrate.

SEMICONDUCTOR DEVICE WITH A LAYERED PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
20190267352 · 2019-08-29 ·

A semiconductor device includes a first die; a second die attached over the first die; a first metal enclosure and a second metal enclosure both directly contacting and vertically extending between the first die and the second die, wherein the first metal enclosure peripherally encircles a set of one or more internal interconnects and the second metal enclosure peripherally encircles the first metal enclosure without directly contacting the first metal enclosure; a first enclosure connector electrically connecting the first metal enclosure to a first voltage level; a second enclosure connector electrically connecting the second metal enclosure to a second voltage level; and wherein the first metal enclosure, the second metal enclosure, the first enclosure connector, and the second enclosure connector are configured to provide an enclosure capacitance.