Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

Various embodiments of the teachings herein include a method for joining and insulating a power electronic semiconductor component with contact surfaces to a substrate. In some embodiments, the method includes: preparing the substrate with a metallization defining an installation slot having joining material, wherein the substrate comprises an organic or a ceramic wiring support; arranging an electrically insulating film and the semiconductor component on the substrate, such that the contact surfaces of the semiconductor component facing the substrate are omitted from the film and regions of the semiconductor component exposed by the contact surfaces are insulated at least in part by the film from the substrate and from the contact surfaces; and joining the semiconductor component to the substrate and electrically insulating the semiconductor component at least in part by the film in one step.

Various embodiments of the teachings herein include a method for joining and insulating a power electronic semiconductor component with contact surfaces to a substrate. In some embodiments, the method includes: preparing the substrate with a metallization defining an installation slot having joining material, wherein the substrate comprises an organic or a ceramic wiring support; arranging an electrically insulating film and the semiconductor component on the substrate, such that the contact surfaces of the semiconductor component facing the substrate are omitted from the film and regions of the semiconductor component exposed by the contact surfaces are insulated at least in part by the film from the substrate and from the contact surfaces; and joining the semiconductor component to the substrate and electrically insulating the semiconductor component at least in part by the film in one step.

Joining a second supporting member to one surface of a semiconductor chip through an upper layer joining portion includes: forming, on the one surface, a pre-joining layer by pressure-sintering a first constituent member containing a sintering material on the one surface such that spaces between the plurality of protrusions are filled with the pre-joining layer and the pre-joining layer has a flat surface on a side of the pre-joining layer away from the semiconductor chip; arranging, on the flat surface, the second supporting member through a second constituent member containing a sintering material; and heating and pressurizing the second constituent member. Thereby, an upper layer joining portion is formed by the second constituent member and the pre-joining layer.

Joining a second supporting member to one surface of a semiconductor chip through an upper layer joining portion includes: forming, on the one surface, a pre-joining layer by pressure-sintering a first constituent member containing a sintering material on the one surface such that spaces between the plurality of protrusions are filled with the pre-joining layer and the pre-joining layer has a flat surface on a side of the pre-joining layer away from the semiconductor chip; arranging, on the flat surface, the second supporting member through a second constituent member containing a sintering material; and heating and pressurizing the second constituent member. Thereby, an upper layer joining portion is formed by the second constituent member and the pre-joining layer.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

Provide is a highly reliable semiconductor device in which stress generated in a semiconductor chip is reduced and an increase in thermal resistance is suppressed. The semiconductor device includes: a semiconductor chip including a first main electrode on one surface thereof and a second main electrode and a gate electrode on the other surface thereof; a first electrode connected to the one surface of the semiconductor chip via a first bonding material; and a second electrode connected to the other surface of the semiconductor chip via a second bonding material. The first electrode is a plate-shaped electrode and has a groove in a region overlapping with the semiconductor chip. The groove penetrates in a thickness direction of the first electrode and reaches an end portion of the first electrode when viewed in a plan view.

Provide is a highly reliable semiconductor device in which stress generated in a semiconductor chip is reduced and an increase in thermal resistance is suppressed. The semiconductor device includes: a semiconductor chip including a first main electrode on one surface thereof and a second main electrode and a gate electrode on the other surface thereof; a first electrode connected to the one surface of the semiconductor chip via a first bonding material; and a second electrode connected to the other surface of the semiconductor chip via a second bonding material. The first electrode is a plate-shaped electrode and has a groove in a region overlapping with the semiconductor chip. The groove penetrates in a thickness direction of the first electrode and reaches an end portion of the first electrode when viewed in a plan view.