A semiconductor device includes an insulating layer having a first surface and a second surface opposite to the first surface. The semiconductor device includes at least one semiconductor element located on a side of the first surface. The semiconductor device includes a first metal sinter and a second metal sinter. The first metal sinter is in contact with the first surface of the insulating layer and the semiconductor element, and bonds the insulating layer and the semiconductor element. The second metal sinter is in contact with the second surface of the insulating layer.

A light-emitting device, including a circuit substrate, a first light-emitting diode, and a first fixing structure, is provided. The circuit substrate includes a substrate, a first pad, a flat layer, and a first electrical connection material. The first pad and the flat layer are located on the substrate. The flat layer has a first opening overlapping the first pad. The first electrical connection material is located in the first opening and is electrically connected to the first pad. The first light-emitting diode is located on the flat layer and in contact with the first electrical connection material. The first fixing structure is located between the first light-emitting diode and the flat layer. The vertical projection of the first fixing structure on the substrate is located in the vertical projection of the first light-emitting diode on the substrate.

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

In one example, a semiconductor device can comprise a unit substrate comprising a unit conductive structure and a unit dielectric structure, and an electronic component coupled to the unit conductive structure. The unit substrate can comprise a portion of a singulated subpanel substrate of a panel substrate. Other examples and related methods are also disclosed herein.

A semiconductor module includes a power element, a signal wiring, and a heat sink. The signal wiring is connected to a signal pad of the power element. The heat sink cools the power element. The power element has an active area provided by a portion where the signal pad is formed. The signal pad is thermally connected to the heat sink via the signal wiring.

Various embodiments may provide a semiconductor package. The semiconductor package may include a first electrical component, a second electrical component, a first heat sink, and a second heat sink bonded to a first package interconnection component and a second package interconnection component. The first package interconnection component and the second package interconnection component may provide lateral and vertical interconnections in the package.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.

An optical module includes an optical semiconductor chip including a first electrode pad, a second electrode pad, and a third electrode pad arranged between the first electrode pad and the second electrode pad, a wiring substrate on which the optical semiconductor chip is flip-chip mounted, including a fourth electrode pad, a fifth electrode pad, and a sixth electrode pad arranged between the fourth electrode pad and the fifth electrode pad, a first conductive material connecting the first electrode pad with the fourth electrode pad, a second conductive material connecting the second electrode pad with the fifth electrode pad, a third conductive material arranged between the first conductive material and the second conductive material, connecting the third electrode pad with the sixth electrode pad, and a resin provided in an area on the second conductive material side of the third conductive material between the optical semiconductor chip and the wiring substrate.

Provide is a highly reliable semiconductor device in which stress generated in a semiconductor chip is reduced and an increase in thermal resistance is suppressed. The semiconductor device includes: a semiconductor chip including a first main electrode on one surface thereof and a second main electrode and a gate electrode on the other surface thereof; a first electrode connected to the one surface of the semiconductor chip via a first bonding material; and a second electrode connected to the other surface of the semiconductor chip via a second bonding material. The first electrode is a plate-shaped electrode and has a groove in a region overlapping with the semiconductor chip. The groove penetrates in a thickness direction of the first electrode and reaches an end portion of the first electrode when viewed in a plan view.