A semiconductor device including a substrate; a chip on which a surface electrode is formed; and a lead. The lead includes a first electrode connecting portion disposed on the surface electrode and electrically connected to the surface electrode of the chip via a conductive bonding material; a second electrode connecting portion electrically connected to an electrode portion of a wiring pattern. A lead connected to the first electrode connecting portion and the second electrode connecting portion. The lead further has a thermal shrinking stress equalizing structure on a portion of an outer periphery of the first electrode connecting portion. The lead is configured to make a thermal shrinking stress applied to a conductive bonding material between the first electrode connecting portion and the surface electrode equal.

A semiconductor device includes: a first chip including first and second electrodes provided at a first surface, and a third electrode provided at a second surface positioned at a side opposite to the first surface; a second chip including fourth and fifth electrodes provided at a third surface, and a sixth electrode provided at a fourth surface positioned at a side opposite to the third surface, wherein the second chip is disposed to cause the third surface to face the first surface; a first connector disposed between the first electrode and the fourth electrode and connected to the first and fourth electrodes; and a second connector disposed between the second electrode and the fifth electrode and connected to the second and fifth electrodes.

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the leadframe top side, and a top notch at the leadframe top side. The top notch includes a top notch base located between the leadframe top side and the leadframe bottom side, and defining a notch length of the top notch, and can also include a top notch first sidewall extended, along the notch length, from the leadframe top side to the top notch base. The first semiconductor die can include a die top side a die bottom side opposite the die top side and mounted onto the leadframe top side, and a die perimeter. The top notch can be located outside the die perimeter. Other examples and related methods are also disclosed herein.

A semiconductor device includes a substrate, a resin case, and a wiring member having an exposed portion adjacent to a first fixing portion fixed in a wall surface of the resin case and exposed to outside, and a second fixing portion fixed in the wall surface of the resin case at a position different from the first fixing portion with respect to a portion extending from the first fixing portion into the resin case, in which the wiring member is bonded to a surface of the semiconductor element by solder in the resin case, and has a plate shape having a length, a thickness, and a width, in which the wiring member has the thickness being uniform and is flat in the resin case, and the width of the second fixing portion is narrower than the width of the exposed portion.

A semiconductor device includes a substrate, a resin case, and a wiring member having an exposed portion adjacent to a first fixing portion fixed in a wall surface of the resin case and exposed to outside, and a second fixing portion fixed in the wall surface of the resin case at a position different from the first fixing portion with respect to a portion extending from the first fixing portion into the resin case, in which the wiring member is bonded to a surface of the semiconductor element by solder in the resin case, and has a plate shape having a length, a thickness, and a width, in which the wiring member has the thickness being uniform and is flat in the resin case, and the width of the second fixing portion is narrower than the width of the exposed portion.

Provided is a semiconductor device including: a transistor portion provided in a semiconductor substrate; and a diode portion provided in the semiconductor substrate, in which an area ratio of the transistor portion to the diode portion on a front surface of the semiconductor substrate is larger than 3.1 and smaller than 4.7. Provided is a semiconductor module including: a semiconductor device including a transistor portion and a diode portion provided in a semiconductor substrate; an external connection terminal electrically connected to the semiconductor device; and a coupling portion for electrically connecting the semiconductor device and the external connection terminal. The coupling portion may be in plane contact with a front surface electrode of the semiconductor device at a predetermined junction surface. An area ratio of the transistor portion to the diode portion may be larger than 2.8 and smaller than 4.7.

This semiconductor device includes: a plate-shaped heat dissipation plate; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal located apart from the heat dissipation plate, extending in a direction away from the heat dissipation plate, and connected via first conductors to surfaces of the switching elements on a side opposite to the heat dissipation plate side; and a sealing member sealing the switching elements, the heat dissipation plate, and the first terminal. A cutout is provided at an outer periphery of the heat dissipation plate. A part of the first terminal on the heat dissipation plate side overlaps a cut-out area at the cutout as seen in a direction perpendicular to the one surface of the heat dissipation plate. A retracted portion retracted inward is formed at an outer periphery of another surface of the heat dissipation plate.

A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.

This semiconductor device includes: a plate-shaped heat dissipation plate; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal located apart from the heat dissipation plate, extending in a direction away from the heat dissipation plate, and connected via first conductors to surfaces of the switching elements on a side opposite to the heat dissipation plate side; and a sealing member sealing the switching elements, the heat dissipation plate, and the first terminal. A cutout is provided at an outer periphery of the heat dissipation plate. A part of the first terminal on the heat dissipation plate side overlaps a cut-out area at the cutout as seen in a direction perpendicular to the one surface of the heat dissipation plate. A retracted portion retracted inward is formed at an outer periphery of another surface of the heat dissipation plate.