A semiconductor chip stack module that includes a substrate, two first semiconductor chips supported by the substrate, and a second semiconductor chip stacked on both of the two first semiconductor chips. The second semiconductor chip is electrically connected to both of the two first semiconductor chips by a conductive paste configured between the second semiconductor chip and both of the two first semiconductor chips. As multiple standard chips are stacked in the power module, and their number as well as the connection methods (e.g. series or parallel) are flexible so that the user can choose which electric characteristic(s) to be increased in the power module with the stacked chips.

First conductive layer is connected to an impurity region which is a source region or an emitter region. A first conductive layer having an emitter pad and a second conductive layer having a Kelvin emitter pad and a relay pad are separated. A plane occupied area of the Kelvin emitter pad is smaller than a plane occupied area of the emitter pad.

An integrated circuit package includes a lead frame, a first die adhered to the lead frame on a first side of the first die, and a first clip having a clip foot adhered to the lead frame. The first clip has a first side and a second side. A first die attachment region is defined by a first group of four notches in the first side of the first clip. The first clip extends from the lead frame and contacts a second side of the first die at the first die attachment region via a first layer of solder paste. The integrated circuit package further has a second die adhered to the second side of the first clip on a first side of the second die, and a second clip having a clip foot adhered to the lead frame. The second clip has a first side and a second side. A second die attachment region is defined by a second group of four notches in the first side of the second clip. The second clip extends from the lead frame and contacts a second side of the second die at the second die attachment region via a second layer of solder paste.

A chip package including a semiconductor chip is provided. The chip package may include a packaging material at least partially around the semiconductor chip with an opening extending from a top surface of the packaging material to the semiconductor chip and/or to an electrical contact structure contacting the semiconductor chip, and a thermally conductive material in the opening, wherein the thermally conductive material is configured to transfer heat from the semiconductor chip to an outside, wherein the thermally conductive material extends laterally at least partially over the top surface of the packaging material.

A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.

A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.

A semiconductor wafer includes: a first main surface and a second main surface opposite the first main surface; a detachment plane parallel to the first main surface inside the semiconductor wafer, the detachment plane defined by defects; electronic semiconductor components formed at the first main surface and between the first main surface and the detachment plane; and a glass structure attached to the first main surface. The glass structure includes openings, each of which leaves a respective area of the electronic semiconductor components uncovered. A method of processing the wafer, a clip, and a semiconductor device are also described.

This semiconductor device is provided with: a semiconductor layer; a cell that is provided on the semiconductor layer; an insulating film that covers the cell; a main electrode part that is superposed on the insulating film; a temperature-sensitive diode for sensing temperatures, the diode having a first electrode and a second electrode; and a connection electrode for diode, the connection electrode being used for the purpose of connecting the first electrode to the outside. The main electrode part has: a first bonding region to which a first conductive member is bonded; and a second bonding region to which a second conductive member is bonded. When viewed from the thickness direction of the semiconductor layer, the cell is provided on both a first semiconductor region in the semiconductor layer, and a second semiconductor region in the semiconductor layer.

A substrate assembly may include a power substrate, a chip, a clip, and a trimetal. The power substrate has a first direct copper bonded (DCB) surface connected to a ceramic tile. The chip is soldered onto the first DCB surface. The clip is attached to the power substrate and has a foot at one end and a recessed area at the other, opposite end. The foot is connected to the power substrate. The trimetal has a base, a trapezoid structure, and a clip portion. The base is soldered to the chip. The trapezoid structure is located above the base. The clip portion is located above the trapezoid structure and includes a projecting area. The recessed area of the clip fits into the projecting area of the trimetal.

A method for fabricating a diode layer stack comprises providing a diode layer stack including a silicon carbide diode die including a first main surface at an anode side of the diode die and a second main surface opposite to the first main surface at a cathode side of the diode die, a layer stack on the first main surface of the diode die, the layer stack including a copper layer disposed on the first main surface of the diode die, and a tin or indium containing layer disposed above the copper layer; providing a die pad comprising a copper leadframe including a first main surface and a second main surface opposite to the first main surface; and performing a diffusion soldering process for connecting the diode layer stack with the layer stack to the first main surface of the die pad.