Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/34
Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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H01L2224/36
Structure, shape, material or disposition of the strap connectors prior to the connecting process
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H01L2224/37
of an individual strap connector
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H01L2224/37693
with a principal constituent of the material being a solid not provided for in groups H01L2224/376 - H01L2224/37691, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
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H01L2224/37693

SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE
20220278039 · 2022-09-01 ·

Provided is a semiconductor module including: an insulating circuit board having a circuit pattern formed in one surface; a semiconductor chip placed in the insulating circuit board; and a wiring portion for electrically connecting the semiconductor chip and the circuit pattern. The wiring portion includes a chip connecting portion connected to the semiconductor chip. A surface of the chip connecting portion includes: a plurality of concave portions; and a flat portion disposed between two concave portions.

SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE
20220278039 · 2022-09-01 ·

Provided is a semiconductor module including: an insulating circuit board having a circuit pattern formed in one surface; a semiconductor chip placed in the insulating circuit board; and a wiring portion for electrically connecting the semiconductor chip and the circuit pattern. The wiring portion includes a chip connecting portion connected to the semiconductor chip. A surface of the chip connecting portion includes: a plurality of concave portions; and a flat portion disposed between two concave portions.