This semiconductor module includes: a base plate formed in a plate shape; a terminal member; an electronic component joined to one surface of the base plate; and mold resin sealing the base plate, the terminal member, and the electronic component. The base plate and the terminal member are conductive members and are arranged with an interval therebetween on the same plane. Each of the base plate and the terminal member has a body portion and a terminal portion exposed to outside from the mold resin. The base plate has a through hole at an extension part which is a part extending toward the terminal portion and connected to the terminal portion, in the body portion.

A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.

A leadframe includes a die pad having arranged thereon a first semiconductor die with an electrically conductive ribbon extending on the first semiconductor die. The first semiconductor die lies intermediate the leadframe and the electrically conductive ribbon. A second semiconductor die is mounted on the electrically conductive ribbon to provide, on the same die pad, a stacked arrangement of the second semiconductor die and the first semiconductor die with the at least one electrically conductive ribbon intermediate the first semiconductor die and the second semiconductor die. Package size reduction can thus be achieved without appreciably affecting the assembly flow of the device.

This semiconductor device includes: a heat dissipation plate formed in a plate shape; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal extending in a direction away from the heat dissipation plate in a state of being apart from the heat dissipation plate, the first terminal being connected via a first electric conductor to surfaces of the plurality of switching elements on an opposite side to the heat dissipation plate side; and a sealing member sealing the plurality of switching elements, the heat dissipation plate, and the first terminal. A notch is provided in an outer periphery portion of the heat dissipation plate. A portion of the first terminal on the heat dissipation plate side overlaps with a region of a cut at the notch as seen in a direction perpendicular to the one surface of the heat dissipation plate.

A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.

A semiconductor device includes metal connector plate having a first lower surface, facing an electrode of a semiconductor chip, a first end surface, a second end surface, and a second lower surface connecting the first end surface and the second end surface. In a first direction parallel to the semiconductor chip, an end surface of the electrode is located between the positions of the first end surface and the second end surface. A distance from the second lower surface to the electrode is greater than a distance from the first lower surface to the electrode. A joining component has a first portion between the first lower surface and the electrode and a second portion between the second lower surface and the electrode.

A semiconductor device includes a chip carrier, a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain when the semiconductor device is operated, a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated, and an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is designed to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other.

In this power semiconductor module, a first lead frame and a second lead frame through which currents flow in opposite directions are arranged so as to overlap each other, whereby the internal inductance can be reduced. In a direction perpendicular to one main surface of a first metal wiring layer, each of the first lead frame and the second lead frame is provided so as not to overlap parts of end surfaces of the first metal wiring layer and a second metal wiring layer. Thus, in a manufacturing process for the power semiconductor module before sealing with sealing resin, it is possible to easily perform positioning between the lead frames and between the metal wiring layer and the lead frame, using the end surfaces, whereby the manufacturing process can be simplified.

A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

An electronic component has a base 10; an electronic element 20 provided on one side of the base 10; a connecting body 30 provided on one side of the electronic element 20; a heat dissipating block 40 provided on one side of the connecting body 30; an insulating part 50 provided between the connecting body 30 and the heat dissipating block 40; and a sealing part 90 in which the electronic element 20, the connecting body 30 and the insulating part 50 are sealed. At least a part of a surface on another side of the base 10 is exposed from the sealing part 90. At least a part of a surface on one side of the heat dissipating block 40 is exposed from the sealing part 90.