Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a package substrate, a redistribution layer on the package substrate, a vertical connection terminals that connects the package substrate to the redistribution layer, a first semiconductor chip between the package substrate and the redistribution layer, a first molding layer that fills a space between the package substrate and the redistribution layer, a second semiconductor chip on the redistribution layer, a third semiconductor chip on the second semiconductor chip, a first connection wire that directly and vertically connects the redistribution layer to a first chip pad of the third semiconductor chip, the first chip pad is beside the second semiconductor chip and on a bottom surface of the third semiconductor chip, and a second molding layer on the redistribution layer and covering the second semiconductor chip and the third semiconductor chip.

A package that includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.

A semiconductor device includes a first wiring substrate having a first surface and a second surface opposite to the first surface, and including a plurality of first electrode pads on the first surface, and a second wiring substrate having a third surface facing the first surface and a fourth surface opposite to the third surface, and including a plurality of second electrode pads on the third surface. A plurality of first semiconductor chips are stacked between the first surface and the third surface. A first columnar electrode extends in an oblique direction with respect to a first direction substantially perpendicular to the first surface and the third surface, and connects between the plurality of first electrode pads and the plurality of second electrode pads. A first resin layer covers the plurality of first semiconductor chips and the first columnar electrode between the first surface and the third surface.

A package that includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.

A fault isolation analysis method includes: providing a package structure in which there is an electrical fault; detecting whether the electrical fault is in interconnecting wires, and if the electrical fault is in the interconnecting wires, determining that the electrical fault is caused by the interconnecting wire; and if the electrical fault is not in the interconnecting wires, breaking the interconnecting wires to electrically isolate the chip structure from the substrate, then detecting whether the electrical fault is in the structure, and if the electrical fault is able to be detected, determining that the electrical fault is caused by the substrate, or if the electrical fault is not able to be detected, determining that the electrical fault is caused by the chip structure.

A manufacturing method of a plated wire rod, the method including: preparing a plated wire rod precursor including a base material that is wire-drawn and that has a linear shape and a plating film that is provided on a surface of the base material, where the base material is made of first metal and the plating film is made of second metal of a different composition from the first metal; obtaining a plated wire rod-intermediate body by performing skin-passing on the plated wire rod precursor using a die; inspecting, after the skin-passing, for presence/absence of a defect in the plated wire rod-intermediate body using an eddy current testing device and a camera inspection device; and obtaining a plated wire rod by removing the defect in the plated wire rod-intermediate body that is detected in the inspecting.

A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler.

A semiconductor device includes a first wiring substrate having a first surface and a second surface opposite to the first surface, and including a plurality of first electrode pads on the first surface, and a second wiring substrate having a third surface facing the first surface and a fourth surface opposite to the third surface, and including a plurality of second electrode pads on the third surface. A plurality of first semiconductor chips are stacked between the first surface and the third surface. A first columnar electrode extends in an oblique direction with respect to a first direction substantially perpendicular to the first surface and the third surface, and connects between the plurality of first electrode pads and the plurality of second electrode pads. A first resin layer covers the plurality of first semiconductor chips and the first columnar electrode between the first surface and the third surface.

A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler.

The invention relates to a heavy-wire bond arrangement, having a substrate (2), a heavy wire (1) and a high-voltage heavy-wire bond connection, in which an end bond section (4) of the heavy wire (1), which extends towards the end (7) of the heavy wire (1), is bonded to the substrate (2), such that in the area of the bond section (4) a bond contact (5) between the heavy wire (1) and the substrate (2) is formed, the heavy wire (1) having a tapering section (6) which adjoins the end of the wire (7) and in which the wire cross-section tapers towards the end of the wire (7). The application additionally relates to a method for producing a heavy-wire bond arrangement.