H01L2224/43985

Apparatus, system, and method for wireless connection in integrated circuit packages
09837340 · 2017-12-05 · ·

Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.

Semiconductor package structure and packaging method thereof

A packaging method includes providing a substrate structure, including a core substrate, a plurality of first conductive pads at a first surface of the core substrate, and a plurality of packaging pads at a second surface of the core substrate; and packaging a plurality of semiconductor chips onto the substrate structure at the second surface of the core substrate, including forming a first metal wire to connect with a chip-contact pad of a semiconductor chip, and forming a molding compound on the second surface of the core substrate to encapsulate the plurality of semiconductor chips. One end of the first metal wire connects to the chip-contact pad, and another end of the first metal wire is exposed at the surface of the molding compound. The packaging method further includes forming a first metal pad on the surface of the molding compound to electrically connect with the first metal wire.

SEMICONDUCTOR PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF
20230343773 · 2023-10-26 ·

A semiconductor package structure includes a substrate, including first conductive pads and packaging pads opposite to the first conductive pads, one or more semiconductor chips stacking on the substrate, a molding compound encapsulating the semiconductor chips, first metal wires connecting the semiconductor chips to the packaging pads, a first metal pad on a side of the molding compound opposite to the substrate, and a second metal wire located in the molding compound and connecting the first metal pad to a chip-contact pad of a semiconductor chip of the semiconductor chips.

SEMICONDUCTOR PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF
20220278089 · 2022-09-01 ·

A packaging method includes providing a substrate structure, including a core substrate, a plurality of first conductive pads at a first surface of the core substrate, and a plurality of packaging pads at a second surface of the core substrate; and packaging a plurality of semiconductor chips onto the substrate structure at the second surface of the core substrate, including forming a first metal wire to connect with a chip-contact pad of a semiconductor chip, and forming a molding compound on the second surface of the core substrate to encapsulate the plurality of semiconductor chips. One end of the first metal wire connects to the chip-contact pad, and another end of the first metal wire is exposed at the surface of the molding compound. The packaging method further includes forming a first metal pad on the surface of the molding compound to electrically connect with the first metal wire.

SYSTEMS AND METHODS FOR HIERARCHICAL EXPOSURE OF AN INTEGRATED CIRCUIT HAVING MULTIPLE INTERCONNECTED DIE
20210167037 · 2021-06-03 ·

A system and method for fabricating distinct types of circuit connections on a semiconductor wafer includes fabricating, using a first photomask, a plurality of a first type of circuit connections for each of a plurality of distinct die of a semiconductor wafer; and fabricating, using a second photomask, a plurality of a second type of circuit connections between a plurality of distinct pairs of components of the semiconductor wafer, wherein each distinct pair of components includes at least one distinct die of the plurality of distinct die and one of a conductive pad and a sacrificial die.

Systems and methods for hierarchical exposure of an integrated circuit having multiple interconnected die
10923456 · 2021-02-16 · ·

A system and method for fabricating distinct types of circuit connections on a semiconductor wafer includes fabricating, using a first photomask, a plurality of a first type of circuit connections for each of a plurality of distinct die of a semiconductor wafer; and fabricating, using a second photomask, a plurality of a second type of circuit connections between a plurality of distinct pairs of components of the semiconductor wafer, wherein each distinct pair of components includes at least one distinct die of the plurality of distinct die and one of a conductive pad and a sacrificial die.

SYSTEMS AND METHODS FOR HIERARCHICAL EXPOSURE OF AN INTEGRATED CIRCUIT HAVING MULTIPLE INTERCONNECTED DIE
20200203308 · 2020-06-25 ·

A system and method for fabricating distinct types of circuit connections on a semiconductor wafer includes fabricating, using a first photomask, a plurality of a first type of circuit connections for each of a plurality of distinct die of a semiconductor wafer; and fabricating, using a second photomask, a plurality of a second type of circuit connections between a plurality of distinct pairs of components of the semiconductor wafer, wherein each distinct pair of components includes at least one distinct die of the plurality of distinct die and one of a conductive pad and a sacrificial die.

METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MANUFACTURED BY THE SAME
20240038720 · 2024-02-01 · ·

A method of manufacturing a semiconductor package of stacked semiconductor chips includes forming a reverse wire bond by bonding one end of a reverse wire to a chip pad of the second-highest semiconductor chip of the stacked semiconductor chips and connecting the other end of the reverse wire to a conductive bump on a chip pad of the uppermost semiconductor chip of the stacked semiconductor chips. The method also includes molding the stacked semiconductor chips with the reverse wire bond using a mold layer. The method further includes processing the mold layer to expose the conductive bump and the other end of the reverse wire in the reverse wire bond through an upper surface of the mold layer.

STRUCTURES AND METHODS FOR CAPACITIVE ISOLATION DEVICES

Described examples include a packaged device including a first object and a second object spaced from each other by a gap, each object having a first surface and an opposite second surface, the first surfaces of the first object and the second object including first terminals. A structure includes at least two conductors embedded in a dielectric casing consolidating a configuration and organization of the at least two conductors, the at least two conductors having end portions un-embedded by the dielectric casing. An end portion of at least one of the at least two conductors is electrically connected to a first terminal of the first object, and an opposite end portion of the at least one of the at least two conductors is electrically connected to a respective first terminal of the second object, the at least two conductors electrically connecting the first object and the second object.

Methods of forming wire interconnect structures and related wire bonding tools

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to a position above the wire bond; (c) moving the wire bonding tool to contact the length of wire, at a position along the length of wire, to partially sever the length of wire at the position along the length of wire; and (d) separating the length of wire from a wire supply at the position along the length of wire, thereby providing a wire interconnect structure bonded to the bonding location.