An object of the present invention is to provide an Ag alloy bonding wire for a semiconductor device capable of extending the high-temperature life of a wire, reducing chip damage during ball bonding, and improving characteristics such as ball bonding strength in applications of on-vehicle memory devices. The Ag alloy bonding wire for a semiconductor device according to the present invention contains one or more of In and Ga for a total of 110 at ppm or more and less than 500 at ppm, and one or more of Pd and Pt for a total of 150 at ppm or more and less than 12,000 at ppm, and a balance being made up of Ag and unavoidable impurities.

Semiconductor chip package device and semiconductor chip package method are provided. The semiconductor chip package device includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves disposed at ends of the lead frame. The chips are electrically connected to the lead frame. The encapsulating layer is formed by using an encapsulating material to encapsulate the chips and at least a portion of the lead frame. The first grooves are filled with the encapsulating material. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

Semiconductor chip package device and semiconductor chip package method are provided. The semiconductor chip package device includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves disposed at ends of the lead frame. The chips are electrically connected to the lead frame. The encapsulating layer is formed by using an encapsulating material to encapsulate the chips and at least a portion of the lead frame. The first grooves are filled with the encapsulating material. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

An object of the present invention is to provide an Ag alloy bonding wire for a semiconductor device capable of extending the high-temperature life of a wire, reducing chip damage during ball bonding, and improving characteristics such as ball bonding strength in applications of on-vehicle memory devices. The Ag alloy bonding wire for a semiconductor device according to the present invention contains one or more of In and Ga for a total of 110 at ppm or more and less than 500 at ppm, and one or more of Pd and Pt for a total of 150 at ppm or more and less than 12,000 at ppm, and a balance being made up of Ag and unavoidable impurities.

Semiconductor chip package device and semiconductor chip package method are provided. The semiconductor chip package device includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves disposed at ends of the lead frame. The chips are electrically connected to the lead frame. The encapsulating layer is formed by using an encapsulating material to encapsulate the chips and at least a portion of the lead frame. The first grooves are filled with the encapsulating material. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

Semiconductor chip package device and semiconductor chip package method are provided. The semiconductor chip package device includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves disposed at ends of the lead frame. The chips are electrically connected to the lead frame. The encapsulating layer is formed by using an encapsulating material to encapsulate the chips and at least a portion of the lead frame. The first grooves are filled with the encapsulating material. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

There is provided a novel Cu bonding wire that achieves a favorable FAB shape and achieve a favorable bond reliability of the 2nd bonding part even in a rigorous high-temperature environment. The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy, and a coating layer having a total concentration of Pd and Ni of 90 atomic% or more formed on a surface of the core material. The bonding wire is characterized in that: in a concentration profile in a depth direction of the wire obtained by performing measurement using Auger electron spectroscopy (AES) so that the number of measurement points in the depth direction is 50 or more for the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, an average value X is 0.2 or more and 35.0 or less where X is defined as an average value of a ratio of a Pd concentration C.sub.Pd (atomic%) to an Ni concentration C.sub.Ni (atomic%), C.sub.Pd/C.sub.Ni, for all measurement points in the coating layer, the total number of measurement points in the coating layer whose absolute deviation from the average value X is 0.3X or less is 50% or more relative to the total number of measurement points in the coating layer, and the bonding wire satisfies at least one of following conditions (i) and (ii): (i) a concentration of In relative to the entire wire is 1 ppm by mass or more and 100 ppm by mass or less; and (ii) a concentration of Ag relative to the entire wire is 1 ppm by mass or more and 500 ppm by mass or less.

There is provided a novel Cu bonding wire that achieves a favorable FAB shape and achieve a favorable bond reliability of the 2nd bonding part even in a rigorous high-temperature environment. The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy, and a coating layer having a total concentration of Pd and Ni of atomic % or more formed on a surface of the core material. The bonding wire is characterized in that: in a concentration profile in a depth direction of the wire obtained by performing measurement using Auger electron spectroscopy (AES) so that the number of measurement points in the depth direction is 50 or more for the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, an average value X is 0.2 or more and 35.0 or less where X is defined as an average value of a ratio of a Pd concentration C.sub.Pd (atomic %) to an Ni concentration C.sub.Ni (atomic %), C.sub.Pd/C.sub.Ni, for all measurement points in the coating layer, the total number of measurement points in the coating layer whose absolute deviation from the average value X is or less is 50% or more relative to the total number of measurement points in the coating layer, and the bonding wire satisfies at least one of following conditions (i) and (ii): (i) a concentration of In relative to the entire wire is 1 ppm by mass or more and 100 ppm by mass or less; and (ii) a concentration of Ag relative to the entire wire is 1 ppm by mass or more and 500 ppm by mass or less.

A portion of a source electrode exposed by an opening in a passivation film is used as a portion of a source pad. A first portion of the source pad includes a plating film formed by a material that is harder than a material of the source electrode. During screening, a probe needle that is a metal contact contacts the plating film that is on the first portion of the source pad. A second portion of the source pad has a layer structure different from that of the first portion of the source pad and in a second direction parallel to the front surface of the semiconductor chip, is disposed adjacently to and electrically connected to the first portion of the source pad. A bonding wire is wire bonded to the second portion of the source pad after an inspection process of the semiconductor chip.

A portion of a source electrode exposed by an opening in a passivation film is used as a portion of a source pad. A first portion of the source pad includes a plating film formed by a material that is harder than a material of the source electrode. During screening, a probe needle that is a metal contact contacts the plating film that is on the first portion of the source pad. A second portion of the source pad has a layer structure different from that of the first portion of the source pad and in a second direction parallel to the front surface of the semiconductor chip, is disposed adjacently to and electrically connected to the first portion of the source pad. A bonding wire is wire bonded to the second portion of the source pad after an inspection process of the semiconductor chip.