A semiconductor device 10 includes a pair of electrodes 16 and a conductive connection member 21 electrically bonded to the pair of electrodes 16. At least a portion of a perimeter of a bonding surface 24 of at least one of the pair of electrodes 16 and the conductive connection member 21 includes an electromigration reducing area 22.

A semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip including a free end portion. Conductive wires respectively electrically connect chip pads of the first semiconductor chips to substrate pads of the package substrate. A plurality of first support structures each have a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip. The first support structures are inclined at an angle relative to the package substrate.

A semiconductor device 10 includes a pair of electrodes 16 and a conductive connection member 21 electrically bonded to the pair of electrodes 16. At least a portion of a perimeter of a bonding surface 24 of at least one of the pair of electrodes 16 and the conductive connection member 21 includes an electromigration reducing area 22.

A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.

A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.

A semiconductor package includes a package substrate including a power pad and a ground pad that are spaced apart from each other in a first horizontal direction, first and second semiconductor chips on the package substrate, the first and second semiconductor chips being stacked in a stepped shape that extends in a second horizontal direction perpendicular to the first horizontal direction, and a plurality of connection wires that electrically connect the package substrate to the first semiconductor chip and/or the second semiconductor chip. The first semiconductor chip includes a plurality of lower option pads. The second semiconductor chip includes a plurality of upper option pads. The plurality of connection wires include a conductive wire that electrically connects at least one of first and second upper chip pads of the second semiconductor chip to at least one of the lower option pads of the first semiconductor chip.

The present invention provides an image sensor module, including an integrated circuit substrate, an image sensing chip, a cover plate and an encapsulating material. The image sensing chip is disposed on the integrated circuit substrate. The image sensing chip includes an image sensing area and a non-image sensing area. A dam is disposed between the cover plate and the non-image sensing area of the image sensing chip. The cover plate includes a transparent material and a cushioning material. The encapsulating material covers the periphery of the image sensing chip, the periphery of the dam, part of the integrated circuit substrate and the periphery of the cover plate. The cushioning material is disposed between the transparent material and the dam and between the transparent material and the encapsulating material. The present invention reduces the possibility that the encapsulating material will peel off the cover plate.

A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.

A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.

A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.