A bonding wire includes a hollow member made of an insulator and mounted such as to bridge ICs formed with interconnects, such that a plurality of open ends is each closed by abutting on a surface of the interconnect that is a connection target, and a connection member made of a conductor, filling inside of the hollow member such as to bond to the surface of the interconnect at a location where the hollow member abuts on the surface of the interconnect.

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

A semiconductor package assembly and method of manufacturing is provided. The assembly includes a semiconductor package and a moulding resin case encapsulating the semiconductor package. The package includes a lead frame having a first frame side and a second frame side opposite to the first frame side; a silicon die structure having a first die side and a second die side opposite to the first side, the silicon die structure being mounted with its second die side on the first frame side of the lead frame; one or more bond wires electrically connecting the silicon die structure with the lead frame; as well as a coating layer covering the semiconductor package from the encapsulating moulding resin case, the coating layer being composed of two or more different amorphous layer coatings. The use of a coating layer covering the complete semiconductor package forming the encapsulating moulding resin case prevents any corrosion.

An optoelectronic semiconductor chip includes a semiconductor layer sequence. The semiconductor layer sequence includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and an active zone having a p-n junction, which active zone is formed between the first semiconductor region and the second semiconductor region. The semiconductor layer sequence is arranged on a carrier. The semiconductor chip also includes a first contact, which is provided for electrically connecting the first semiconductor region, and a second contact, which is different from the first contact and which is provided for electrically connecting the second semiconductor region. In addition, the semiconductor chip includes a first capacitive electrical element, which is connected in parallel with the p-n junction and which has a first dielectric element.

An optoelectronic semiconductor chip includes a semiconductor layer sequence. The semiconductor layer sequence includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and an active zone having a p-n junction, which active zone is formed between the first semiconductor region and the second semiconductor region. The semiconductor layer sequence is arranged on a carrier. The semiconductor chip also includes a first contact, which is provided for electrically connecting the first semiconductor region, and a second contact, which is different from the first contact and which is provided for electrically connecting the second semiconductor region. In addition, the semiconductor chip includes a first capacitive electrical element, which is connected in parallel with the p-n junction and which has a first dielectric element.

An optoelectronic component includes a housing including a plastic material and a first lead frame section at least partly embedded in the plastic material, a first recess and a second recess, wherein a first upper section of an upper side of the first lead frame section is not covered by the plastic material in the first recess, a second upper section of the upper side of the first lead frame section is not covered by the plastic material in the second recess, the first recess and the second recess are separated from one another by a section of the plastic material, an optoelectronic semiconductor chip is arranged in the first recess, and no optoelectronic semiconductor chips is arranged in the second recess.

An optoelectronic component includes a housing including a plastic material and a first lead frame section at least partly embedded in the plastic material, a first recess and a second recess, wherein a first upper section of an upper side of the first lead frame section is not covered by the plastic material in the first recess, a second upper section of the upper side of the first lead frame section is not covered by the plastic material in the second recess, the first recess and the second recess are separated from one another by a section of the plastic material, an optoelectronic semiconductor chip is arranged in the first recess, and no optoelectronic semiconductor chips is arranged in the second recess.

A radiation-emitting semiconductor device includes at least one semiconductor chip having a semiconductor layer sequence having an active region that produces radiation; a mounting surface on which at least one electrical contact for external contacting of the semiconductor chip is formed, wherein the mounting surface runs parallel to a main extension plane of the semiconductor layer sequence; a radiation exit surface running at an angle to or perpendicularly to the mounting surface; a radiation-guiding layer arranged in a beam path between the semiconductor chip and the radiation exit surface; and a reflector body adjacent to the radiation-guiding layer in regions and in a top view of the semiconductor device covers the semiconductor chip.

A radiation-emitting semiconductor device includes at least one semiconductor chip having a semiconductor layer sequence having an active region that produces radiation; a mounting surface on which at least one electrical contact for external contacting of the semiconductor chip is formed, wherein the mounting surface runs parallel to a main extension plane of the semiconductor layer sequence; a radiation exit surface running at an angle to or perpendicularly to the mounting surface; a radiation-guiding layer arranged in a beam path between the semiconductor chip and the radiation exit surface; and a reflector body adjacent to the radiation-guiding layer in regions and in a top view of the semiconductor device covers the semiconductor chip.

A power semiconductor contact structure for power semiconductor modules, which has at least one substrate 1 and a metal moulded body 2 as an electrode, which are sintered one on top of the other by means of a substantially uninterrupted sintering layer 3a with regions of varying thickness. The metal moulded body 2 takes the form here of a flexible contacting film 5 of such a thickness that this contacting film is sintered with its side 4 facing the sintering layer 3a onto the regions of varying thickness of the sintering layer substantially over the full surface area. A description is also given of a method for forming a power semiconductor contact structure in a power semiconductor module that has a substrate and a metal moulded body. The forming of the power semiconductor contact structure is performed firstly by applying a layer of sintering material of locally varying thickness to either the metal moulded body 2 or the substrate, followed by sintering together the contacting film 5 with the substrate 1 by using the properties of the layer of sintering material that are conducive to connection, the contacting film 5 being made to develop its distinct form to correspond to the varying thickness of the layer of sintering material 3a.