A semiconductor device includes a substrate, an active region provided in the substrate, a plurality of gate fingers provided on the active region, extending in an extension direction, and arranged in an arrangement direction orthogonal to the extension direction, and a gate connection wiring commonly connected to the plurality of gate fingers and provided between the plurality of gate fingers and a first side surface of the substrate, wherein when viewed from the arrangement direction, a first position where a first end of a first gate finger as a part of the plurality of gate fingers is connected to the gate connection wiring is closer to the first side surface than a second position where a first end of a second gate finger as another part of the plurality of gate fingers is connected to the gate connection wiring.

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die.

Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view.

A resin having a small linear thermal expansion coefficient and a low absorbance is provided. The resin is characterized by including at least one structure selected from structures represented by the following general formulae (1) and (2):

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A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

A thermosetting silicone resin composition contains the following components (A-1) to (D): (A-1) an alkenyl group-containing linear organopolysiloxane; (A-2) a branched organopolysiloxane shown by (R.sup.1.sub.3SiO.sub.1/2).sub.a(R.sup.2.sub.3SiO.sub.1/2).sub.b(SiO.sub.4/2).sub.c (1); (B-1) a branched organohydrogenpolysiloxane shown by (HR.sup.2.sub.2SiO.sub.1/2).sub.d(R.sup.2.sub.3SiO.sub.1/2).sub.e(SiO.sub.4/2).sub.f (2); (B-2) a linear organohydrogenpolysiloxane shown by (R.sup.2.sub.3SiO.sub.1/2).sub.2(HR.sup.2SiO.sub.2/2).sub.x(R.sup.2.sub.2SiO.sub.2/2).sub.y (3); (C) an adhesion aid which is an epoxy group-containing branched organopolysiloxane; and (D) a catalyst containing a combination of a zero-valent platinum complex with a divalent platinum complex and/or a tetravalent platinum complex. This provides a thermosetting silicone resin composition which causes little contamination at a gold pad portion and has excellent adhesiveness to a silver lead frame.

A method of manufacturing a semiconductor device is provided. The method includes attaching a first end of a first bond wire to a first conductive lead and a second end of the first bond wire to a first bond pad of a first semiconductor die. A conductive lead extender is affixed to the first conductive lead by way of a conductive adhesive, the lead extender overlapping the first end of the first bond wire. A first end of a second bond wire is attached to the lead extender, the first end of the second bond wire conductively connected to the first end of the first bond wire.

A semiconductor device includes a pad formed on a surface of a substrate, a bonding wire for connecting the pad to an external circuit, and a resin layer covering at least a connection portion between the pad and the bonding wire and exposing at least a part of the substrate outside the pad.

A semiconductor device including an element isolation in a trench formed in an upper surface of a semiconductor substrate, a trench isolation including a void in a trench directly under the element isolation, and a Cu wire with Cu ball connected to a pad on the semiconductor substrate, is formed. The semiconductor device has a circular trench isolation arrangement prohibition region that overlaps the end portion of the Cu ball in plan view, and the trench isolation is separated from the trench isolation arrangement prohibition region in plan view.