A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.

A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.

A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.

A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.

A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.

A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.

A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.

A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.

A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps. The electronic package includes a leadframe having a plurality of leads, wherein each of the leads has a lead tip, an opening formed within the leadframe, a die paddle that is disposed within the opening and is isolated from each of the lead tips, a tape that is adhered to a back side of the leadframe, leads, and die paddle, and a die, wherein the die is attached to the die paddle and is connected by wires to a bump disposed on each of the lead tips.

A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps. The electronic package includes a leadframe having a plurality of leads, wherein each of the leads has a lead tip, an opening formed within the leadframe, a die paddle that is disposed within the opening and is isolated from each of the lead tips, a tape that is adhered to a back side of the leadframe, leads, and die paddle, and a die, wherein the die is attached to the die paddle and is connected by wires to a bump disposed on each of the lead tips.