An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film. The metal film is made of one or more metals selected from the group consisting of Pd, Au, Ru, Rh, Pt, and Ir.

Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction.

An electrical circuit in a semiconductor package may include a wire connected at each end by a bond point formed using a wire-bonding machine. When a connection point (e.g., a die pad) has a very small dimension, the wire used for the circuit may be required to have a similarly small diameter. This small diameter can lead to a weak bond point, especially in bonds that include a heel portion. The heel portion is a transition region of the bond point that may have less strength (e.g., as measure by a pull-test) than other portions of the bond point and/or may be exposed to more forces than other portions of the bond point. Accordingly, a capping-bond point may be applied to the bond point to strengthen the bond point by clamping the heel portion and shielding it from forces that could cause cracks.

A microelectronic structure (200) and a fabrication method of microelectronic are described. A first package (10) has a first conductive pad (40, 41, 47, 48) formed on a first foundation layer (12). A loop of conductive wire (50-53) is wirebonded to the first conductive pad ((40, 41, 47, 48) of the first foundation layer (12). A mold cap (70) is formed on the first foundation layer (12). A via (90-93) is formed in the mold cap (70) to reach the conductive wire (50-53). A solder structure (80-83) is coupled to the conductive wire (50-53). A second package (100) is connected to the first package (10) by attaching a second solder structure (110-113) of a second package (100) to the first solder structure (80-83) of the first package (10).

Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction.

A microelectronic structure (200) and a fabrication method of microelectronic are described. A first package (10) has a first conductive pad (40, 41, 47, 48) formed on a first foundation layer (12). A loop of conductive wire (50-53) is wirebonded to the first conductive pad ((40, 41, 47, 48) of the first foundation layer (12). A mold cap (70) is formed on the first foundation layer (12). A via (90-93) is formed in the mold cap (70) to reach the conductive wire (50-53). A solder structure (80-83) is coupled to the conductive wire (50-53). A second package (100) is connected to the first package (10) by attaching a second solder structure (110-113) of a second package (100) to the first solder structure (80-83) of the first package (10).

This disclosure provides a package substrate and its fabrication method. The package substrate includes: a dielectric body; a first circuit device disposed in the dielectric body, the first circuit device comprising a first terminal and a second terminal at a top of the first circuit device; a second circuit device disposed in the dielectric body, the second circuit device comprising a third terminal at a top of the second circuit device; a first conductive pillar formed in the dielectric body and connected to the first terminal; a first bonding wire connecting the second terminal and the third terminal; and a redistribution layer comprising a first conductive wire formed on the dielectric body, the conductive wire connected to the first conductive pillar.

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.

A semiconductor device includes a plurality of wire bonds formed on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; a protective material is applied around the plurality of wire bonds, the protective material having a first pH; and at least a portion of the semiconductor device and the protective material are encapsulated with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.