In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/10 degrees.

An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/10 degrees.

In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/10 degrees.

An integrated circuit package includes a substrate having a first surface and a second surface. An electronic integrated circuit chip has a first surface and a second surface, with the second surface mounted on the first surface of the substrate. A preformed glass cover is assembled on the first surface of the substrate and arranged to contain the electronic integrated circuit chip.

An integrated circuit (IC) package includes an interconnect comprising patches of unoxidized metal that are circumscribed by a region of roughened metal formed of oxidized metal. The IC package also includes a die mounted on the interconnect. The die is conductively coupled to at least a subset of the patches of unoxidized metal.

A semiconductor chip includes a semiconductor substrate including a die region, and a peripheral region surrounding the die region; a device layer on the die region, the device layer including semiconductor devices and wiring layers; a peripheral protective layer surrounding the device layer on the peripheral region; and connection pads on an upper surface of the device layer and adjacent to one side of the upper surface of the device layer, wherein a side surface of the semiconductor substrate adjacent to the one side of the upper surface of the device layer includes protruding portions located at both corners and a recess surface indented into the die region between the protruding portions.

An integrated circuit (IC) package includes an interconnect comprising patches of unoxidized metal that are circumscribed by a region of roughened metal formed of oxidized metal. The IC package also includes a die mounted on the interconnect. The die is conductively coupled to at least a subset of the patches of unoxidized metal.