The semiconductor device includes a supporting member, a conductive member, and a semiconductor element. The supporting member has a supporting surface facing in a thickness direction. The conductive member has an obverse surface facing the same side as the supporting surface faces in the thickness direction, and a reverse surface opposite to the obverse surface. The conductive member is bonded to the supporting member such that the reverse surface faces the supporting surface. The semiconductor element is bonded to the obverse surface. The semiconductor device further includes a first metal layer and a second metal layer. The first metal layer covers at least a part of the supporting surface. The second metal layer covers the reverse surface. The first metal layer and the second layer are bonded to each other by solid phase diffusion.

An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.

The semiconductor device includes a supporting member, a conductive member, and a semiconductor element. The supporting member has a supporting surface facing in a thickness direction. The conductive member has an obverse surface facing the same side as the supporting surface faces in the thickness direction, and a reverse surface opposite to the obverse surface. The conductive member is bonded to the supporting member such that the reverse surface faces the supporting surface. The semiconductor element is bonded to the obverse surface. The semiconductor device further includes a first metal layer and a second metal layer. The first metal layer covers at least a part of the supporting surface. The second metal layer covers the reverse surface. The first metal layer and the second layer are bonded to each other by solid phase diffusion.

A transistor device includes a semiconductor substrate having a first major surface and transistor cells formed therein. Each transistor cell includes a drift region of a first conductivity type, a body region of an opposing second conductivity type arranged on the drift region, a source region of the first conductivity type arranged on the body region, a columnar field plate trench extending into the first major surface and including a field plate, and a gate trench structure extending into the first major surface and including a gate electrode. A first metallization structure on the first major surface provides a first contact pad for wire bonding. At least one of depth and doping level of the body region is locally increased within the transistor cells located within one or more first areas of the first major surface. One or more of the first areas are located underneath the first contact pad.

A power electronics arrangement, comprising an electrical conduction section, and a switching device which, in operation, switches the electrical conduction section. The switching device includes multiple parallel connected semiconductor switches which are triggered in common by a plurality of lead wires from a control unit and are switched across respective ones of the lead wire upon reaching a switching state of charge. Each of the lead wires has a same electrical resistance, and a different length.

A package that includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.

Implementations of a semiconductor package system may include a first bond wire bonded to a portion of a leadframe and to a pad of a semiconductor die, the first bond wire coupled to one of a power source or a ground; and a second bond wire bonded to the portion of the leadframe and to a control integrated circuit. The portion of the leadframe may form a current sense area and the control integrated circuit may be configured to use the second bond wire and the current sense area to measure a current flowing through the first bond wire during operation.

A semiconductor device includes: a semiconductor element having an element main surface and an element back surface spaced apart from each other in a thickness direction, and including a plurality of main surface electrodes arranged on the element main surface; a die pad on which the semiconductor element is mounted; a plurality of leads including at least one first lead arranged on one side in a first direction orthogonal to the thickness direction with respect to the die pad, and arranged around the die pad when viewed in the thickness direction; a plurality of connecting members including a first connecting member, and configured to electrically connect the plurality of main surface electrodes and the plurality of leads; and a resin member configured to seal the semiconductor element, a part of the die pad, parts of the plurality of leads, and the plurality of connecting members.

A semiconductor device includes: a semiconductor element having an element main surface and an element back surface spaced apart from each other in a thickness direction and including a plurality of main surface electrodes arranged on the element main surface; a die pad on which the semiconductor element is mounted; a plurality of leads including at least one first lead and at least one second lead and arranged around the die pad when viewed in the thickness direction; a plurality of connecting members including a first connecting member and a second connecting member and configured to electrically connect the plurality of main surface electrodes and the plurality of leads; and a resin member configured to seal the semiconductor element, a part of the die pad, parts of the plurality of leads, and the plurality of connecting members and having a rectangular shape when viewed in the thickness direction.

A semiconductor device, includes: a semiconductor element having element main surface and element back surface spaced apart from each other in thickness direction and including a plurality of main surface electrodes arranged on the element main surface; a die pad having a die pad main surface where the semiconductor element is mounted; a plurality of leads including at least one first lead arranged on one side in first direction orthogonal to the thickness direction with respect to the die pad, and arranged around the die pad when viewed in the thickness direction; a plurality of connecting members including a first connecting member bonded to the at least one first lead, and configured to electrically connect the main surface electrodes and the leads; and a resin member configured to seal the semiconductor element, a part of the die pad, parts of the leads, and the connecting members