The present application discloses a chip socket, a testing fixture and a chip testing method thereof. The chip socket includes a pedestal, a plurality of conductive traces, a plurality of clamp structures, and a plurality of electrical contacts. The plurality of conductive traces are formed in the pedestal. The plurality of clamp structures are conductive and disposed on the first surface of the pedestal, and at least one of the plurality of clamp structures is coupled to a corresponding conductive trace and configured to clamp a solder ball of a chip to be tested. The plurality of electrical contacts are disposed on the second surface of the pedestal, and at least one of the plurality of electrical contacts is coupled to a corresponding clamp structure through a corresponding conductive trace.

An electrical connector allowing a connection between two substantially facing electrical contacts respectively pertaining to a housing and a support, and including a main body including a first end for secure connection thereof to the housing and a second end for secure connection thereof to the support, the main body being bent in at least one bending area.

The present application discloses a chip socket, a testing fixture and a chip testing method thereof. The chip socket includes a pedestal, a plurality of conductive traces, a plurality of clamp structures, and a plurality of electrical contacts. The plurality of conductive traces are formed in the pedestal. The plurality of clamp structures are conductive and disposed on the first surface of the pedestal, and at least one of the plurality of clamp structures is coupled to a corresponding conductive trace and configured to clamp a solder ball of a chip to be tested. The plurality of electrical contacts are disposed on the second surface of the pedestal, and at least one of the plurality of electrical contacts is coupled to a corresponding clamp structure through a corresponding conductive trace.

An electrical connector allowing a connection between two substantially facing electrical contacts respectively pertaining to a housing and a support, and including a main body including a first end for secure connection thereof to the housing and a second end for secure connection thereof to the support, the main body being bent in at least one bending area.

The present application discloses a chip socket, a testing fixture and a chip testing method thereof. The chip socket includes a pedestal, a plurality of conductive traces, a plurality of clamp structures, and a plurality of electrical contacts. The plurality of conductive traces are formed in the pedestal. The plurality of clamp structures are conductive and disposed on the first surface of the pedestal, and at least one of the plurality of clamp structures is coupled to a corresponding conductive trace and configured to clamp a solder ball of a chip to be tested. The plurality of electrical contacts are disposed on the second surface of the pedestal, and at least one of the plurality of electrical contacts is coupled to a corresponding clamp structure through a corresponding conductive trace.

The present application discloses a chip socket, a testing fixture and a chip testing method thereof. The chip socket includes a pedestal, a plurality of conductive traces, a plurality of clamp structures, and a plurality of electrical contacts. The plurality of conductive traces are formed in the pedestal. The plurality of clamp structures are conductive and disposed on the first surface of the pedestal, and at least one of the plurality of clamp structures is coupled to a corresponding conductive trace and configured to clamp a solder ball of a chip to be tested. The plurality of electrical contacts are disposed on the second surface of the pedestal, and at least one of the plurality of electrical contacts is coupled to a corresponding clamp structure through a corresponding conductive trace.

Some implementations herein provide a semiconductor package and methods of formation. The semiconductor package includes a semiconductor die having a first set of conductive structures connected with a substrate having a second set of conductive structures, where a profile of heights of the second set of conductive structures includes a curvature relative to a surface of the substrate. The curvature is configured to compensate for warpage (e.g., offset warpage) that may be induced to the semiconductor die and/or the substrate during a reflow process that joins the semiconductor die and the substrate. By compensating for the warpage, a planarity of an interface region including solder joints between the first and second sets of conductive structures is increased. Increasing the planarity may reduce solder joint defects in the semiconductor package relative to another semiconductor package including another substrate having conductive structures without the profile having the curvature.