A method of adjusting a clamping of a semiconductor element against a support structure on a wire bonding machine is provided. The method includes: (a) detecting an indicia of floating of the semiconductor element with respect to the support structure at a plurality of locations of the semiconductor element; and (b) adjusting the clamping of the semiconductor element against the support structure based on the results of step (a).

A method of adjusting a clamping of a semiconductor element against a support structure on a wire bonding machine is provided. The method includes: (a) detecting an indicia of floating of the semiconductor element with respect to the support structure at a plurality of locations of the semiconductor element; and (b) adjusting the clamping of the semiconductor element against the support structure based on the results of step (a).

A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.

A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.

A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.

A method of adjusting a clamping of a semiconductor element against a support structure on a wire bonding machine is provided. The method includes: (a) detecting an indicia of floating of the semiconductor element with respect to the support structure at a plurality of locations of the semiconductor element; and (b) adjusting the clamping of the semiconductor element against the support structure based on the results of step (a).

A method of manufacturing a semiconductor package that includes: disposing a semiconductor chip on a support board; sealing the semiconductor chips with a sealant to form a sealed body on the support board, thereby forming sealed semiconductor chips; and forming a rewiring layer and bumps on a side where the semiconductor chip is disposed, after the support board is removed from the sealed body The method also includes an individualizing step of cutting the sealed body along regions corresponding to division lines on the support board, to perform individualization in such a manner that the sealed semiconductor chips each have an upper surface and a lower surface larger than the upper surface, with a side wall inclined from the upper surface toward the lower surface; and a step of forming a conductive shield layer on the upper surfaces and the side walls of the plurality of sealed semiconductor chips.

A method of manufacturing a semiconductor package includes: bonding a plurality of semiconductor chips to a plurality of mounting regions on a wiring board partitioned by crossing streets; supplying a liquid resin to a front surface side of the wiring board onto which the plurality of semiconductor chips have been bonded, to seal the plurality of semiconductor chips in a collective manner, thereby forming a sealed board; cutting the sealed board along the regions corresponding to the streets, to individualize the sealed chips in such a manner that the sealed chips each have an upper surface and a lower surface larger than the upper surface, with a side surface inclined from the upper surface toward the lower surface; and forming a conductive shield layer on the upper surfaces and the side surfaces of the plurality of sealed chips.

A ribbon bonding tool is provided. The ribbon bonding tool includes a body portion including a tip portion, the tip portion defining a working surface. The ribbon bonding tool includes a group of four protrusions extending from the working surface, wherein the working surface defines four quadrants in a horizontal plane by extending an imaginary line at a midpoint along each of a length and a width of the working surface. Each of the four protrusions is arranged in one of four quadrants.

A method of adjusting a clamping of a semiconductor element against a support structure on a wire bonding machine is provided. The method includes: (a) detecting an indicia of floating of the semiconductor element with respect to the support structure at a plurality of locations of the semiconductor element; and (b) adjusting the clamping of the semiconductor element against the support structure based on the results of step (a).