A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

A heterogeneous chip stacking structure includes a first chip and a second chip. The first chip has a plurality of first convex pillar structures gradually formed outward from the first chip within a first predetermined time, and each of the first convex pillar structures has a first bonding pad portion. The second chip has a plurality of second convex pillar structures gradually formed outward from the second chip within a second predetermined time, and each of the second convex pillar structures has a second bonding pad portion. The first chip is configured to be disposed on the second chip, and the first bonding pad portions of the first convex pillar structures of the first chip and the second bonding pad portions of the second convex pillar structures of the second chip are in direct contact with each other and tightly coupled with each other, respectively.

A heterogeneous chip stacking method includes providing a first chip, in which the first chip has a plurality of first convex pillar structures, and each first convex pillar structure has a first bonding pad portion; providing a second chip different from the first chip, in which the second chip has a plurality of second convex pillar structures, and each second convex pillar structures having a second bonding pad portion; placing the first chip on the second chip, in which the first bonding pad portions of the first convex pillar structures and the second bonding pad portions of the second convex pillar structures are in direct contact with each other respectively; and then applying at least one of a predetermined pressure, a predetermined temperature, and a predetermined ultrasonic frequency to tightly couple the first bonding pad portions and the second bonding pad portions with each other respectively.

A heterogeneous chip stacking device includes a substrate carrying structure, a position-limiting substrate structure, a first cover structure, a second cover structure and a chip carrying structure. The position-limiting substrate structure is detachably disposed on the substrate carrying structure. The first cover structure is detachably disposed above the position-limiting substrate structure. The second cover structure is detachably disposed on the first cover structure. The chip carrying structure is movably disposed above the substrate carrying structure. The position-limiting substrate structure has a plurality of position-limiting grooves for respectively accommodating a plurality of first chips. The first cover structure is disposed on the first chips to press the first chips, and the first cover structure has a plurality of first openings configured to respectively accommodate a plurality of second chips. The second cover structure has a plurality of second openings configured to respectively communicate with the first openings.