A die bonding method includes obtaining information about a quality grade of each die of a plurality of dies placed at a wafer, picking up a first die among the plurality of dies from the wafer, identifying a bonding location of a plurality of bonding locations from a substrate according to a quality grade of the first die, and bonding the first die to the bonding location of the substrate.

A pick and place method and apparatus thereof are provided. The pick and place method includes: providing at least one semiconductor element disposed on a source storage location; picking up the at least one semiconductor element from the source storage location; transferring the at least one semiconductor element to a temporary storage device according to a signal; positioning the at least one semiconductor element through the temporary storage device; and picking up the positioned semiconductor element from the temporary storage device and placing the positioned semiconductor element on a destination storage location.

A system for assembling fields from a source substrate onto a second substrate. The source substrate includes fields. The system further includes a transfer chuck that is used to pick at least four of the fields from the source substrate in parallel to be transferred to the second substrate, where the relative positions of the at least four of the fields is predetermined.

A wafer bonding device includes: a first fixing apparatus fixing a first wafer, on which a first alignment mark is disposed; a second fixing apparatus fixing a second wafer, on which a second alignment mark is disposed, the second fixing apparatus being disposed opposite to the first fixing apparatus; a reflection member between the first and second fixing apparatuses; a mark reader which reads position information about the first and second alignment marks by means of the reflection member, for aligning the first wafer with the second wafer; and a heating apparatus, configured to heat the first wafer or the second wafer to thermally expand the first wafer or the second wafer so that the first alignment mark or the second alignment mark is located at a central position of a field of view of the mark reader. A wafer bonding method also is involved.

Methods and systems for improving fusion bonding are disclosed. Plasma treatment is performed on a substrate prior to the fusion bonding, which leaves residual charge on the substrate to be fusion bonded. The residual charge is usually dissipated through an electrically conductive silicone cushion on a loading pin. In the methods, the amount of residual voltage on a test silicon wafer is measured. If the residual voltage is too high, this indicates the usable lifetime of the silicone cushion has passed, and the electrically conductive silicone cushion is replaced. This ensures the continued dissipation of residual charge during use in production, improving the quality of fusion bonds between substrates.

In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.

A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

A bonding device measures a position deviation amount of the chip with respect to the substrate in a state where the chip and the substrate are in contact, and corrects and moves the chip relatively to the substrate in such a way as to reduce the position deviation amount, based on the measured position deviation amount. Then, the bonding device fixes the chip to the substrate by irradiating a resin portion of the chip with an ultraviolet ray and curing the resin portion when the position deviation amount of the chip with respect to the substrate is equal to or less than a position deviation amount threshold value.

A bonding tool and a bonding method are provided. The method includes attaching a semiconductor die to a bonding tool having a first surface, wherein the bonding tool comprises a bending member movably arranged in a trench of the bonding tool, and the bending member protrudes from the first surface and bends the semiconductor die; moving the semiconductor die toward a semiconductor wafer to cause a retraction of the bending member and a partial bonding at a portion of the semiconductor die and the semiconductor wafer; and causing a full bonding between the semiconductor die and the semiconductor wafer subsequent to the partial bonding.

Provided is a hybrid bonding apparatus including a plurality of chambers, and a transferer configured to transfer a plurality of wafers between the plurality of chambers and transfer a plurality of bonded wafers to an annealing chamber, the plurality of wafers including a plurality of substrate wafers and a plurality of die supply wafers, wherein the plurality of chambers respectively includes a wafer supplier configured to store the plurality of wafers, a bonding device configured to bond the plurality of wafers, the bonding device including a bonder configured to bond dies on the plurality of substrate wafers from the plurality of die supply wafers, and a pre-annealing oven configured to primarily anneal the plurality of substrate wafers, and a processor.