A package substrate film including a film substrate including upper and lower surfaces; a test pattern including an upper test line pattern extending on the upper surface of the film substrate; a lower test line pattern extending on the lower surface of the film substrate; a first test via pattern penetrating the film substrate and connecting the upper test line pattern to the lower test line pattern; a second test via pattern penetrating the film substrate outside the first test via pattern and connecting the upper test line pattern to the lower test line pattern; and a test pad between the first test via pattern and the second test via pattern, the test pad including first test pad at an outer side of the first test via pattern; and second test pad at an inner side of the second test via pattern and facing the first test pad.

A package substrate film including a film substrate including upper and lower surfaces; a test pattern including an upper test line pattern extending on the upper surface of the film substrate; a lower test line pattern extending on the lower surface of the film substrate; a first test via pattern penetrating the film substrate and connecting the upper test line pattern to the lower test line pattern; a second test via pattern penetrating the film substrate outside the first test via pattern and connecting the upper test line pattern to the lower test line pattern; and a test pad between the first test via pattern and the second test via pattern, the test pad including first test pad at an outer side of the first test via pattern; and second test pad at an inner side of the second test via pattern and facing the first test pad.

In an embodiment a method includes providing a semiconductor chip having a plurality of contact pins, at least one positioning pin and an underside, wherein the contact pins and the positioning pin protrude from the underside, respectively, wherein the contact pins are configured for making electrical contact with the semiconductor chip, wherein the positioning pin narrows in a direction away from the underside, and wherein the positioning pin protrudes further from the underside than the contact pins, providing a connection carrier having a plurality of contact recesses, at least one positioning recess and an upper side, wherein each contact recess is at least partially filled with a solder material, heating the solder material in the contact recesses to a joining temperature at which the solder material at least partially melts and placing the semiconductor chip on the connection carrier, wherein each contact pin is inserted into a contact recess and the positioning pin is inserted into the positioning recess.

In an embodiment a method includes providing a semiconductor chip having a plurality of contact pins, at least one positioning pin and an underside, wherein the contact pins and the positioning pin protrude from the underside, respectively, wherein the contact pins are configured for making electrical contact with the semiconductor chip, wherein the positioning pin narrows in a direction away from the underside, and wherein the positioning pin protrudes further from the underside than the contact pins, providing a connection carrier having a plurality of contact recesses, at least one positioning recess and an upper side, wherein each contact recess is at least partially filled with a solder material, heating the solder material in the contact recesses to a joining temperature at which the solder material at least partially melts and placing the semiconductor chip on the connection carrier, wherein each contact pin is inserted into a contact recess and the positioning pin is inserted into the positioning recess.

In one embodiment, an integrated circuit assembly includes a substrate comprising electrical connectors on a top side of the substrate and an integrated circuit die coupled to the top side of the substrate. The integrated circuit die includes metal pillars extending from a bottom side of the die facing the top side of the substrate, and the metal pillars of the integrated circuit die are electrically connected to the electrical connectors of the substrate via a liquid metal (e.g., a Gallium-based alloy).

A semiconductor package device is provided. The semiconductor package device includes a circuit substrate having a first terminal end; a chip disposed on the circuit substrate and having a conductive pad; an auxiliary structure disposed between the first terminal end and the conductive pad, wherein the chip is electrically connected to the circuit substrate through the auxiliary structure; and a protective layer disposed on the circuit substrate and surrounding the chip, wherein the width of the first terminal end is greater than or equal to the width of the auxiliary structure.