Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.

A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.