According to one embodiment, a semiconductor device includes: a printed wiring substrate that includes a substrate, a wiring layer on the substrate, and a first insulating layer on the wiring layer. The wiring layer includes a connection terminal and a wiring electrically connected to the connection terminal. The first insulating layer includes an opening that exposes at least a portion of the connection terminal and at least a portion of the wiring, and at least one of a protrusion portion or a recess portion, provided along an edge of the opening, that overlaps the wiring. The semiconductor device includes a semiconductor chip mounted on the printed wiring substrate; a bonding wire that electrically connects the connection terminal and the semiconductor chip; and a second insulating layer that covers the semiconductor chip, the bonding wire, and the opening.

According to one embodiment, a semiconductor device includes: a printed wiring substrate that includes a substrate, a wiring layer on the substrate, and a first insulating layer on the wiring layer. The wiring layer includes a connection terminal and a wiring electrically connected to the connection terminal. The first insulating layer includes an opening that exposes at least a portion of the connection terminal and at least a portion of the wiring, and at least one of a protrusion portion or a recess portion, provided along an edge of the opening, that overlaps the wiring. The semiconductor device includes a semiconductor chip mounted on the printed wiring substrate; a bonding wire that electrically connects the connection terminal and the semiconductor chip; and a second insulating layer that covers the semiconductor chip, the bonding wire, and the opening.

According to one embodiment, a semiconductor device includes: a printed wiring substrate that includes a substrate, a wiring layer on the substrate, and a first insulating layer on the wiring layer. The wiring layer includes a connection terminal and a wiring electrically connected to the connection terminal. The first insulating layer includes an opening that exposes at least a portion of the connection terminal and at least a portion of the wiring, and at least one of a protrusion portion or a recess portion, provided along an edge of the opening, that overlaps the wiring. The semiconductor device includes a semiconductor chip mounted on the printed wiring substrate; a bonding wire that electrically connects the connection terminal and the semiconductor chip; and a second insulating layer that covers the semiconductor chip, the bonding wire, and the opening.

According to one embodiment, a semiconductor device includes: a printed wiring substrate that includes a substrate, a wiring layer on the substrate, and a first insulating layer on the wiring layer. The wiring layer includes a connection terminal and a wiring electrically connected to the connection terminal. The first insulating layer includes an opening that exposes at least a portion of the connection terminal and at least a portion of the wiring, and at least one of a protrusion portion or a recess portion, provided along an edge of the opening, that overlaps the wiring. The semiconductor device includes a semiconductor chip mounted on the printed wiring substrate; a bonding wire that electrically connects the connection terminal and the semiconductor chip; and a second insulating layer that covers the semiconductor chip, the bonding wire, and the opening.

Embodiments relate to the design of a device capable of increasing the electrical performance of an interconnect feature by amplifying the current carrying capacity of an interconnect feature. The device comprises a first body comprising a first surface with at least one nanoporous conductive structure protruding from the first surface. The device further comprises a second body comprising a second surface with arrays of nanofibers extending from the second surface and penetrating into corresponding nanoporous conductive structures to form conductive pathways between the first body and the second body.

Embodiments relate to the design of a device capable of increasing the electrical performance of an interconnect feature by amplifying the current carrying capacity of an interconnect feature. The device comprises a first body comprising a first surface with at least one nanoporous conductive structure protruding from the first surface. The device further comprises a second body comprising a second surface with arrays of nanofibers extending from the second surface and penetrating into corresponding nanoporous conductive structures to form conductive pathways between the first body and the second body.