A display device including: a substrate including pixel electrodes; a passivation layer on the substrate, a groove in the passivation layer between the pixel electrodes;

contact electrodes on the pixel electrodes; and a light-emitting element layer comprising a plurality of light-emitting elements respectively bonded onto the contact electrodes and having a plurality of semiconductor layers thereon. The groove does not overlap the plurality of light-emitting elements.

A semiconductor packaging structure manufactured in a manner which does not leave the chip damaged or susceptible to damage upon the removal of temporary manufacturing supports includes at least one electrical conductor, at least one conductive layer, a chip, and a colloid. The chip is spaced from the conductive layer, the electrical conductor is disposed between the conductive layer and the chip and electrically connects the conductive layer to the chip. The colloid covers all outer surfaces of the chip. A method of fabricating such a semiconductor packaging structure is also provided.

The present disclosure provides a package device and a manufacturing method thereof. The package device includes an electronic device, a conductive pad having a first bottom surface, and a redistribution layer disposed between the conductive pad and the electronic device. The redistribution layer has a second bottom surface, and the conductive pad is electrically connected to the electronic device through the redistribution layer. The first bottom surface is closer to the electronic device than the second bottom in a normal direction of the electronic device.

A semiconductor package is provided, including a package component and a number of conductive features. The package component has a non-planar surface. The conductive features are formed on the non-planar surface of the package component. The conductive features include a first conductive feature and a second conductive feature respectively arranged in a first position and a second position of the non-planar surface. The height of the first position is less than the height of the second position, and the size of the first conductive feature is smaller than the size of the second conductive feature.

A semiconductor package is provided, including a package component and a number of conductive features. The package component has a non-planar surface. The conductive features are formed on the non-planar surface of the package component. The conductive features include a first conductive feature and a second conductive feature respectively arranged in a first position and a second position of the non-planar surface. The height of the first position is less than the height of the second position, and the size of the first conductive feature is smaller than the size of the second conductive feature.

A system includes a semiconductor substrate having a first cavity. The semiconductor substrate forms a pedestal adjacent the first cavity. A device overlays the pedestal and is bonded to the semiconductor substrate by metal within the first cavity. A plurality of second cavities are formed in a surface of the pedestal beneath the device, wherein the second cavities are smaller than the first cavity. In some of these teachings, the second cavities are voids. In some of these teachings, the metal in the first cavity comprises a eutectic mixture. The structure relates to a method of manufacturing in which a layer providing a mask to etch the first cavity is segmented to enable easy removal of the mask-providing layer from the area over the pedestal.

A method of using an optoelectronic semiconductor stamp to manufacture an optoelectronic semiconductor device comprises the following steps: a preparation step: preparing at least one optoelectronic semiconductor stamp group and a target substrate, wherein each optoelectronic semiconductor stamp group comprises at least one optoelectronic semiconductor stamp, each optoelectronic semiconductor stamp comprises a plurality of optoelectronic semiconductor components disposed on a heat conductive substrate, each optoelectronic semiconductor component has at least one electrode, and the target substrate has a plurality of conductive portions; an align-press step: aligning and attaching at least one optoelectronic semiconductor stamp to the target substrate, so that the electrodes are pressed on the corresponding conductive portions; and a bonding step: electrically connecting the electrodes to the corresponding conductive portions.

A method for forming a semiconductor structure includes following operations. A first substrate including a first side, a second side opposite to the first side, and a metallic pad disposed over the first side is received. A dielectric structure including a first trench directly above the metallic pad is formed. A second trench is formed in the dielectric structure and a portion of the first substrate. A sacrificial layer is formed to fill the first trench and the second trench. A third trench is formed directly above the metallic pad. A barrier ring and a bonding structure are formed in the third trench. A bonding layer is disposed to bond the first substrate to a second substrate. A portion of the second side of the first substrate is removed to expose the sacrificial layer. The sacrificial layer is removed by an etchant.

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

In an embodiment a method for producing a semiconductor component comprising at least one semiconductor chip mounted on a surface, wherein the semiconductor chip is fixed on the surface by applying a solder compound to an assembling surface of the semiconductor chip, applying a metallic adhesive layer to a side of the solder compound facing away from the assembling surface, preheating the surface to a first temperature T1, bringing the metallic adhesive layer into mechanical contact in a solid state with the preheated surface, the metallic adhesive layer at least partially melting while it is brought into mechanical contact with the preheated surface, and subsequently cooling the surface to room temperature, the semiconductor chip being at least partially metallurgically bonded to the surface, and wherein the semiconductor chip is subsequently soldered to the surface to form a resulting solder connection.