A method for forming a semiconductor structure includes following operations. A first substrate including a first side, a second side opposite to the first side, and a metallic pad disposed over the first side is received. A dielectric structure including a first trench directly above the metallic pad is formed. A second trench is formed in the dielectric structure and a portion of the first substrate. A sacrificial layer is formed to fill the first trench and the second trench. A third trench is formed directly above the metallic pad. A barrier ring and a bonding structure are formed in the third trench. A bonding layer is disposed to bond the first substrate to a second substrate. A portion of the second side of the first substrate is removed to expose the sacrificial layer. The sacrificial layer is removed by an etchant.

Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.

The invention concerns an electrical connection pad (10′) for providing an electrical connection between components of an electronic system, wherein the electrical connection pad comprises: a metallic layer (12); and a laser induced periodic surface structure (20), LIPSS, formed on an external surface (16) of the electrical connection pad (10) and exposing the metallic layer (12) and a method for correspondingly laser-treating an electrical connection pad (10).

The invention concerns an electrical connection pad (10′) for providing an electrical connection between components of an electronic system, wherein the electrical connection pad comprises: a metallic layer (12); and a laser induced periodic surface structure (20), LIPSS, formed on an external surface (16) of the electrical connection pad (10) and exposing the metallic layer (12) and a method for correspondingly laser-treating an electrical connection pad (10).

A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.

A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate.