A method of and device for making a three dimensional electronic circuit. The method comprises coupling one or more magnet wires with a substrate along a surface contour of the substrate, immobilizing the one or more magnet wires on the substrate, and forming the electronic circuit by electrically coupling the one or more magnet wires with an integrated circuit chip.

A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.

A chip for hybrid bridged fanout chiplet connectivity, the chip comprising: a central chiplet; one or more first chiplets each coupled to the central chiplet using a plurality of fanout traces; and one or more second chiplets each coupled to the central chiplet using one or more interconnect dies (ICDs).

A chip for hybrid bridged fanout chiplet connectivity, the chip comprising: a central chiplet; one or more first chiplets each coupled to the central chiplet using a plurality of fanout traces; and one or more second chiplets each coupled to the central chiplet using one or more interconnect dies (ICDs).

A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.

A method for producing an electric circuit in which a contact carrier comprising a first contact area and a second contact area is provided. An insulating body is applied to the circuit carrier and at least partially covers the first contact area and the second contact area. The insulating body comprises cut-outs in regions both contact areas. A flowable electrical conducting medium is introduced into the insulating body.

The present disclosure provides a microcontroller unit and its fabrication method. The microcontroller unit includes a logic control substrate, and also includes at least one memory die and at least one non-memory die, which are disposed on the logic control substrate. The logic control substrate includes a semiconductor device layer and an interconnection dielectric layer. A central processing unit and at least one logic controller are formed in the semiconductor device layer. All memory dies are disposed on the interconnection dielectric layer side by side or stacked one over another, and the at least one memory die is electrically connected to the central processing unit through a corresponding electrical interconnection structure in the interconnection dielectric layer. All non-memory dies are disposed on the interconnection dielectric layer side by side or stacked one over another and are electrically connected to corresponding logic controllers through corresponding electrical interconnection structures in the interconnection dielectric layer.

The present disclosure provides a microcontroller unit and its fabrication method. The microcontroller unit includes a logic control substrate, and also includes at least one memory die and at least one non-memory die, which are disposed on the logic control substrate. The logic control substrate includes a semiconductor device layer and an interconnection dielectric layer. A central processing unit and at least one logic controller are formed in the semiconductor device layer. All memory dies are disposed on the interconnection dielectric layer side by side or stacked one over another, and the at least one memory die is electrically connected to the central processing unit through a corresponding electrical interconnection structure in the interconnection dielectric layer. All non-memory dies are disposed on the interconnection dielectric layer side by side or stacked one over another and are electrically connected to corresponding logic controllers through corresponding electrical interconnection structures in the interconnection dielectric layer.

The invention relates to a method (20) for producing an electric circuit (2) in which a circuit carrier (4) comprising a first contact surface (14) and a second contact surface (16) is provided. An insulating body (26) is placed on the circuit carrier (4), wherein the insulating body (26) at least partially covers the first contact surface (14) and the second contact surface (16), and the insulating body (26) comprises a recess (34) in the region of both contact surfaces (14, 16). A flowable electro-conductive medium (44) is introduced into the insulating body (26). The invention also relates to an electric circuit (2) and to a further method (60) for producing an electric circuit (2).

Disclosed is a back-to-back three-dimensional stacked fan-out packaging structure and a preparation method thereof, and also a packaging module utilizing the packaging structure and a preparation method thereof. The solution provided by the present invention does not require chip TSV stacking, and the stacked chips may be electrically connected in the shortest vertical interconnection manner, thereby ensuring a high interconnection density and transmission performance while reducing packaging costs and improving packaging yield.