In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

Embodiments may relate to a method of forming a microelectronic package with an integrated heat spreader (IHS). The method may include placing a solder thermal interface material (STIM) layer on a face of a die that is coupled with a package substrate; coupling the IHS with the STIM layer and the package substrate such that the STIM is between the IHS and the die; performing formic acid fluxing of the IHS, STIM layer, and die; and dispensing, subsequent to the formic acid fluxing, sealant on the package substrate around a periphery of the IHS.

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

Embodiments of the present disclosure relate to methods of fabricating IC devices with IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure, as well as resulting IC devices, assemblies, and systems. An example method includes providing a semiconductor material over a semiconductor support structure and, subsequently, depositing a first bonding material on the semiconductor material. The method further includes depositing a second bonding material on a non-semiconductor support structure such as glass or mica wafers, followed by bonding the face of the semiconductor material with the first bonding material to the face of the non-semiconductor support structure with the second bonding material. Using first and second bonding materials that include silicon, nitrogen, and oxygen (e.g., silicon oxynitride or carbon-doped silicon oxynitride) may significantly improve bonding between semiconductor layers and non-semiconductor support structures compared to layer transfer techniques.

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

In a semiconductor device according to the present disclosure, one end and the other end of a plurality of insulation covering wires are joined to a connection region in an upper electrode of a DBC substrate over a semiconductor element while an insulation covering portion in a center region has contact with a surface of the semiconductor element. The plurality of insulation covering wires are provided along an X direction in the same manner as the plurality of metal wires. The plurality of insulation covering wires are provided with no loosening, thus have press force of pressing the semiconductor element in a direction of the solder joint portion.

A method includes forming a first tacking layer on a first connection partner, arranging a first layer on the first tacking layer, forming a second tacking layer on the first layer, arranging a second connection partner on the second tacking layer, heating the tacking layers and first layer, and pressing the first connection partner towards the second connection partner, with the first layer arranged between the connection partners, such that a permanent mechanical connection is formed between the connection partners. Either the tacking layers each include a second material evenly distributed within a first material, the second material being configured to act as or to release a reducing agent, or the tacking layers each include a mixture of at least a third material and a fourth material, the materials in the mixture chemically reacting with each other under the influence of heat such that a reducing agent is formed.

Disclosed herein is an electrical connecting structure having nano-twins copper, including a first substrate having a first nano-twins copper layer and a second substrate having a second nano-twins copper layer. The first nano-twins copper layer includes a plurality of first nano-twins copper grains. The second nano-twins copper layer includes a plurality of second nano-twins copper grains. The first nano-twins copper layer is joined with the second nano-twins copper layer. At least a portion of the first nano-twins copper grains extend into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains extend into the first nano-twins copper layer.

Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact is formed above the first device layer. A first capping layer is formed at an upper end of the first bonding contact. The first capping layer has a conductive material different from a remainder of the first bonding contact. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact is formed above the second device layer. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact by the first capping layer.