A bonded structure includes a semiconductor element, an electrical conductor and a sintered metal layer. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a first direction and includes a reverse-surface electrode on the element reverse surface. The electrical conductor has a mount surface facing in a same direction as the element obverse surface and supports the semiconductor element with the mount surface facing the element reverse surface. The sintered metal layer bonds the semiconductor element to the electrical conductor and electrically connects the reverse-surface electrode and the electrical conductor. The mount surface includes a roughened area roughened by a roughening process. The sintered metal layer is formed on the roughened area.

Provided is a semiconductor device capable of accurately positioning a semiconductor element with respect to a metal circuit pattern or positioning an insulating substrate with respect to a base plate without using a dedicated positioning jig, thereby being able to be manufactured inexpensively and a method of manufacturing the semiconductor device. The semiconductor device includes: an insulating substrate; and a semiconductor element, wherein the insulating substrate includes an insulating layer and a metal circuit pattern provided on an upper surface of the insulating layer, the semiconductor element is solder joined to an upper surface of the metal circuit pattern, and an oxide film or a nitride film is provided in a region where the semiconductor element is not solder joined in the upper surface of the metal circuit pattern.

A bonded structure includes a semiconductor element, an electrical conductor and a sintered metal layer. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a first direction and includes a reverse-surface electrode on the element reverse surface. The electrical conductor has a mount surface facing in a same direction as the element obverse surface and supports the semiconductor element with the mount surface facing the element reverse surface. The sintered metal layer bonds the semiconductor element to the electrical conductor and electrically connects the reverse-surface electrode and the electrical conductor. The mount surface includes a roughened area roughened by a roughening process. The sintered metal layer is formed on the roughened area.

An integrated circuit packaging method, including: a top surface of a substrate, a bottom surface of the substrate, or the interior of the substrate is provided with circuit layers, and the circuit layers are provided with circuit pins; a component element is mounted on the substrate, and a surface of the component element facing the substrate is provided with component pins; connection through holes are formed on the substrate, the connection through holes are made to abut on the circuit pins, and a first opening of the connection through holes is abutted on the component pins; conductive layers are fabricated inside of the connection through holes by means of a second opening of the connection through holes, and the conductive layers electrically connect the component pins with the circuit pins.

A chip connection method and structure are provided. The method includes: providing a first connection line and a second connection line on a substrate, wherein, in the thickness direction of the substrate, a distance between the first connection line and the chip is smaller than a distance between the second connection line and the chip; providing the chip on a top surface of the substrate, the chip being provided with at least two chip pins; and providing the substrate with a second through hole corresponding to the second connecting line and provided therein with a second conductive layer, at least one chip pin being electrically connected to the first connection line, and at least one of the remaining chip pin being corresponding to a first opening of the second through, and the second conductive layer electrically connecting the chip pin and the second connection line.

A video wall module includes a plurality of light emitting diode chips, each including first contact electrodes and second contact electrodes arranged at a contact side, wherein the light emitting diode chips are arranged at a top side of a multilayer circuit board, and the contact electrodes electrically conductively connect to a first metallization layer arranged at the top side of the circuit board.

A method for minimizing an average surface includes: forming an epitaxial layer on a growth substrate; forming the soft metal layer on the epitaxial layer in which the average surface roughness of a bonding surface of the soft metal layer is greater than a first value; forming a glue layer on a carrier substrate; placing a combination of the glue layer and the carrier substrate on the bonding surface in which the glue layer being in contact with the bonding surface of the soft metal layer; and performing a laser lift-off process to separate the growth substrate from the epitaxial layer such that the average surface roughness of the bonding surface of the soft metal layer is reduced to be less than a second value. The second value is smaller than the first value, and the second value is less than 80 nm.

An integrated circuit packaging method, including: a top surface of a substrate, a bottom surface of the substrate, or the interior of the substrate is provided with circuit layers, and the circuit layers are provided with circuit pins; a component element is mounted on the substrate, and a surface of the component element facing the substrate is provided with component pins; connection through holes are formed on the substrate, the connection through holes are made to abut on the circuit pins, and a first opening of the connection through holes is abutted on the component pins; conductive layers are fabricated inside of the connection through holes by means of a second opening of the connection through holes, and the conductive layers electrically connect the component pins with the circuit pins.

A chip connection method and structure are provided. The method includes: providing a first connection line and a second connection line on a substrate, wherein, in the thickness direction of the substrate, a distance between the first connection line and the chip is smaller than a distance between the second connection line and the chip providing the chip on a top surface of the substrate, the chip being provided with at least two chip pins; and providing the substrate with a second through hole corresponding to the second connecting line, and provided therein with a second conductive layer, at least one chip pin being electrically connected to the first connection line, and at least one of the remaining chip pin being corresponding to a first opening of the second through hole, and the second conductive layer electrically connecting the chip pin and the second connection line.

One or more chips are transferred from one substrate to another by using one or more polymer layers to secure the one or more chips to an intermediate carrier substrate. While secured to the intermediate carrier substrate, the one or more chips may be transported or put through further processing or fabrication steps. To release the one or more chips, the adhesion strength of the one or more polymer layers is gradually reduced to minimize potential damage to the one or more chips.