A method for manufacturing an electronic component includes preparing a mounting substrate provided with a first region to mount an electronic component thereon and a second region having conductivity, covering the second region with resin, applying a metal paste on the first region, mounting the electronic component on the first region with the metal paste, and removing the resin covering the second region. The mounting includes heating the mounting substrate to cure the metal paste with the electronic components being placed on the metal paste applied on the first region. The resin peeled from the second region by the heating is removed in the removing.

Disclosed herein is an electrical connecting structure having nano-twins copper, including a first substrate having a first nano-twins copper layer and a second substrate having a second nano-twins copper layer. The first nano-twins copper layer includes a plurality of first nano-twins copper grains. The second nano-twins copper layer includes a plurality of second nano-twins copper grains. The first nano-twins copper layer is joined with the second nano-twins copper layer. At least a portion of the first nano-twins copper grains extend into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains extend into the first nano-twins copper layer.

In a semiconductor device according to the present disclosure, one end and the other end of a plurality of insulation covering wires are joined to a connection region in an upper electrode of a DBC substrate over a semiconductor element while an insulation covering portion in a center region has contact with a surface of the semiconductor element. The plurality of insulation covering wires are provided along an X direction in the same manner as the plurality of metal wires. The plurality of insulation covering wires are provided with no loosening, thus have press force of pressing the semiconductor element in a direction of the solder joint portion.

Process for producing an electronic subassembly by low-temperature pressure sintering, comprising the following steps: arranging an electronic component on a circuit carrier having a conductor track, connecting the electronic component to the circuit carrier by the low-temperature pressure sintering of a joining material which connects the electronic component to the circuit carrier, characterized in that, to avoid the oxidation of the electronic component or of the conductor track, the low-temperature pressure sintering is carried out in a low-oxygen atmosphere having a relative oxygen content of 0.005 to 0.3%.

A sintering paste includes solvent and nanomicrocrystallite (NMC) particles. Each NMC particle is a single crystallite having at least one dimension in the range of 1 nm to 100 nm and at least one dimension in the range of 0.1 μm to 1000 μm. The sintering paste may be used in a pressureless sintering process to form a low porosity joint having high bond strength, high electrical and thermal conductivity, and high thermal stability.

Process for producing an electronic subassembly by low-temperature pressure sintering, comprising the following steps: arranging an electronic component on a circuit carrier having a conductor track, connecting the electronic component to the circuit carrier by the low-temperature pressure sintering of a joining material which connects the electronic component to the circuit carrier, characterized in that, to avoid the oxidation of the electronic component or of the conductor track, the low-temperature pressure sintering is carried out in a low-oxygen atmosphere having a relative oxygen content of 0.005 to 0.3%.

A material includes a base resin; a solvent; and a foaming agent and a photosensitizer, and/or a substance that serves as a foaming agent and a photosensitizer.

The present invention addresses the problem of providing a conductive paste that achieves both low resistance and high adhesion strength (die shear strength) of the resulting conductive body after firing.

The present invention provides a conductive paste comprising: (A) copper fine particles having an average particle diameter of 50 nm to 400 nm and a crystallite diameter of 20 nm to 50 nm; (B) copper particles having an average particle diameter of 0.8 μm to 5 μm and a ratio of a crystallite diameter to the crystallite diameter of the copper particles (A) of 1.0 to 2.0; and (C) a solvent.

Disclosed herein is an electrical connecting structure having nano-twins copper, including a first substrate having a first nano-twins copper layer and a second substrate having a second nano-twins copper layer. The first nano-twins copper layer includes a plurality of first nano-twins copper grains. The second nano-twins copper layer includes a plurality of second nano-twins copper grains. The first nano-twins copper layer is joined with the second nano-twins copper layer. At least a portion of the first nano-twins copper grains extend into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains extend into the first nano-twins copper layer.

A method of manufacturing a semiconductor device which includes a plurality of members including a semiconductor element is provided. The method may include disposing one surface of a first member which is one of the plurality of members and one surface of a second member which is another one of the plurality of members opposite to each other with a tin-based (Sn-based) solder material interposed therebetween, and bonding the first member and the second member by melting and solidifying the Sn-based solder material. At least the one surface of the first member may be constituted of a nickel-based (Ni-based) metal, and at least the one surface of the second member may be constituted of copper (Cu).