The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10.sup.−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10.sup.−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10.sup.−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10.sup.−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

A semiconductor device includes: a seal portion; a first electronic element; a first lead terminal; a second lead terminal having one end that is disposed to be close to the one end of the first lead terminal within the seal portion, and another end that is exposed from another end of the seal portion, the other end of the seal portion being along the longitudinal direction; a first connecting element disposed within the seal portion, and having one end that is electrically connected to the first electrode disposed on the first electronic element, and another end that is electrically connected to the one end of the second lead terminal; and a conductive bonding agent.

A semiconductor device includes: a seal portion; a first electronic element; a first lead terminal; a second lead terminal having one end that is disposed to be close to the one end of the first lead terminal within the seal portion, and another end that is exposed from another end of the seal portion, the other end of the seal portion being along the longitudinal direction; a first connecting element disposed within the seal portion, and having one end that is electrically connected to the first electrode disposed on the first electronic element, and another end that is electrically connected to the one end of the second lead terminal; and a conductive bonding agent.

A semiconductor device includes a semiconductor element, leads, and an encapsulation resin covering a portion of each of the leads and the semiconductor element. Each of the leads includes an external connection portion projecting from a side surface of the encapsulation resin. The external connection portion of at least one of the leads has opposite ends in a width-wise direction that extends along the side surface of the encapsulation resin. The external connection portion includes two recesses arranged toward a center in the width-wise direction from the opposite ends. The two recesses extend from a distal surface toward the encapsulation resin. The opposite ends in the width-wise direction define an end connection part. The external connection portion includes a part between the two recesses defining a center connection part.

A semiconductor device includes a semiconductor element, leads, and an encapsulation resin covering a portion of each of the leads and the semiconductor element. Each of the leads includes an external connection portion projecting from a side surface of the encapsulation resin. The external connection portion of at least one of the leads has opposite ends in a width-wise direction that extends along the side surface of the encapsulation resin. The external connection portion includes two recesses arranged toward a center in the width-wise direction from the opposite ends. The two recesses extend from a distal surface toward the encapsulation resin. The opposite ends in the width-wise direction define an end connection part. The external connection portion includes a part between the two recesses defining a center connection part.

A semiconductor device includes a semiconductor body; an electrode provided on the semiconductor body and electrically connected to the semiconductor body; a first metal layer selectively provided on the electrode; an insulating layer surrounding the first metal layer on the electrode; and a second metal layer provided on the first metal layer. The insulating layer includes a first surface and a second surface adjacent to the first surface. The first surface contacts a top surface of the first metal layer at an outer edge of the first metal layer. The second metal layer has an outer edge contacting the second surface of the insulating layer.

A semiconductor device includes a semiconductor body; an electrode provided on the semiconductor body and electrically connected to the semiconductor body; a first metal layer selectively provided on the electrode; an insulating layer surrounding the first metal layer on the electrode; and a second metal layer provided on the first metal layer. The insulating layer includes a first surface and a second surface adjacent to the first surface. The first surface contacts a top surface of the first metal layer at an outer edge of the first metal layer. The second metal layer has an outer edge contacting the second surface of the insulating layer.