A power module is provided. The power module includes a substrate, a power conversion chip that is disposed on the substrate and an insulating film that is formed on a structure in which the power conversion chip is disposed on the substrate. Additionally, the power module includes a metal mold that encases the structure that is coated with the insulating film. Additionally, the power module provides a simplified structure and improved heat dissipation performance compared to conventional power modules.

An object of the present invention is to suppress a crack in a sealing resin and a warpage in a semiconductor device in a power semiconductor device. A power semiconductor device includes: a semiconductor element; a terminal; a chassis; and a sealing resin sealing the semiconductor element and the terminal in the chassis. The sealing resin includes: a first sealing resin covering at least the semiconductor element; and a second sealing resin formed on an upper portion of the first sealing resin, and in an operation temperature of the semiconductor element, the first sealing resin has a smaller linear expansion coefficient than the second sealing resin, and a difference of a linear expansion coefficient between the first sealing resin and the terminal is smaller than a difference of a linear expansion coefficient between the second sealing resin and the terminal.

A semiconductor module is provided with a conductive member having one end, in a longitudinal direction, joined to an electrode of a semiconductor element that is mounted on an insulating substrate, the other end of the conductive member in the longitudinal direction being joined to a component different from the electrode. The conductive member is made up of a metal sheet, and has a bent portion at the one end and at the other end. The bent portion provided at the one end has a cut in a leading end portion, in the longitudinal direction, and an end joining section at which the cut is not present is joined to the electrode of the semiconductor element. As a result, a semiconductor module can be realized that allows combination of increased current capacity with improved reliability.

A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

A semiconductor module is provided, including: a semiconductor chip having an upper surface electrode and a lower surface electrode opposite to the upper surface electrode; a metal wiring plate electrically connected to the upper surface electrode of the semiconductor chip; and a sheet-like low elastic sheet provided on the metal wiring plate, the low elastic sheet having elastic modulus lower than that of the metal wiring plate. A manufacturing method for a semiconductor module is provided, including: providing a semiconductor chip; solder-bonding a metal wiring plate above said semiconductor chip; and applying a sheet-like low elastic sheet having the elastic modulus lower than that of said metal wiring plate to said metal wiring plate.

A semiconductor device in which a semiconductor element mounted on a laminate substrate and an electrically conductive connection member are sealed with a sealing material, includes: a primer layer in an interface between the sealing material and sealed members including the laminate substrate, the semiconductor element, and the electrically conductive connection member, in which the sealing material includes a first sealing layer which is provided in contact with the primer layer; and a second sealing layer which covers the first sealing layer, the semiconductor device satisfies α.sub.p≥α.sub.1>α.sub.2 in which α.sub.p, α.sub.1, and α.sub.2 represent coefficients of linear thermal expansion of the primer layer, the first sealing layer, and the second sealing layer, respectively, α.sub.c≥15×10.sup.−6/° C. in which α.sub.c represents a composite coefficient of linear thermal expansion of the sealing layers, and E.sub.c≥5 GPa or more in which E.sub.c represents a composite Young's modulus of the sealing layers.

A semiconductor device in which a semiconductor element mounted on a laminate substrate and an electrically conductive connection member are sealed with a sealing material, includes: a primer layer in an interface between the sealing material and sealed members including the laminate substrate, the semiconductor element, and the electrically conductive connection member, in which the sealing material includes a first sealing layer which is provided in contact with the primer layer; and a second sealing layer which covers the first sealing layer, the semiconductor device satisfies α.sub.p≥α.sub.1>α.sub.2 in which α.sub.p, α.sub.1, and α.sub.2 represent coefficients of linear thermal expansion of the primer layer, the first sealing layer, and the second sealing layer, respectively, α.sub.c≥15×10.sup.−6/° C. in which α.sub.c represents a composite coefficient of linear thermal expansion of the sealing layers, and E.sub.c≥5 GPa or more in which E.sub.c represents a composite Young's modulus of the sealing layers.

The invention relates to a method for electrically contacting a component (10) (for example a power component and/or a (semiconductor) component having at least one transistor, preferably an IGBT (insulated-gate bipolar transistor)) having at least one contact (40, 50), at least one open-pored contact piece (60, 70) is galvanically (electrochemically or free of external current) connected to at least one contact (40, 50). In this way, a component module is achieved. The contact (40, 50) is preferably a flat part or has a contact surface, the largest planar extent thereof being greater than an extension of the contact (40, 50) perpendicular to said contact surface. The temperature of the galvanic connection is at most 100° C., preferably at most 60° C., advantageously at most 20° C. and ideally at most 5° C. and/or deviates from the operating temperature of the component by at most 50° C., preferably by at most 20° C., in particular by at most 10° C. and ideally by at most 5° C., preferably by at most 2° C. The component (10) can be contacted by means of the contact piece (60, 70) with a further component, a current conductor and/or a substrate (90). Preferably, a component (10) having two contacts (40, 50) on opposite sides of the component (10) is used, wherein at least one open-pored contact piece (60, 70) is galvanically connected to each contact (40, 50).

The present disclosure is directed to improving package adhesion to provide more reliable semiconductor packages. The semiconductor package may be, for example, a leadframe including one or multiple dies attached thereto. The semiconductor package may include only clip bonds or only wire bonds or a combination of clip bonds and wire bonds. An adhesion enhancement coating may be disposed in between the package substrate and the encapsulant to improve package adhesion. For example, the adhesion enhancement coating enhances the sealing by bonding respectively with the inorganic materials of the package substrate and the organic materials of the encapsulant.

A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.