Patent classifications
H01L2224/85125
Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
METHODS FOR GENERATING WIRE LOOP PROFILES FOR WIRE LOOPS, AND METHODS FOR CHECKING FOR ADEQUATE CLEARANCE BETWEEN ADJACENT WIRE LOOPS
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A bonding region is specified by having a horizontal line partially constituting crosshairs displayed on a monitor of a wire bonding apparatus superimposed on a first line segment of a first marker, and having a vertical line partially constituting the crosshairs superimposed on a first line segment of a second marker.
METHODS FOR GENERATING WIRE LOOP PROFILES FOR WIRE LOOPS, AND METHODS FOR CHECKING FOR ADEQUATE CLEARANCE BETWEEN ADJACENT WIRE LOOPS
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A bonding region is specified by having a horizontal line partially constituting crosshairs displayed on a monitor of a wire bonding apparatus superimposed on a first line segment of a first marker, and having a vertical line partially constituting the crosshairs superimposed on a first line segment of a second marker.
METHODS FOR GENERATING WIRE LOOP PROFILES FOR WIRE LOOPS, AND METHODS FOR CHECKING FOR ADEQUATE CLEARANCE BETWEEN ADJACENT WIRE LOOPS
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.