Patent classifications
H01L2224/85127
SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS MANUFACTURING METHOD
A semiconductor apparatus includes a semiconductor element, a control terminal electrically connected to a top electrode of the semiconductor element through a wiring member, and a case member in which at least a portion of the control terminal is embedded and which defines a space for housing the semiconductor element. The control terminal includes a pad to which the wiring member is connected. The case member includes a wiring member positioning part raised on the case member as a reference point for a positioning of the wiring member before a connection is made of the wiring member to the pad.
Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
METHODS FOR GENERATING WIRE LOOP PROFILES FOR WIRE LOOPS, AND METHODS FOR CHECKING FOR ADEQUATE CLEARANCE BETWEEN ADJACENT WIRE LOOPS
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
METHODS FOR GENERATING WIRE LOOP PROFILES FOR WIRE LOOPS, AND METHODS FOR CHECKING FOR ADEQUATE CLEARANCE BETWEEN ADJACENT WIRE LOOPS
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
METHODS FOR GENERATING WIRE LOOP PROFILES FOR WIRE LOOPS, AND METHODS FOR CHECKING FOR ADEQUATE CLEARANCE BETWEEN ADJACENT WIRE LOOPS
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.